Abstract: A wireless media distribution system is provided comprising an access point (6) for broadcasting media and a plurality of stations (2) for reception and playback of media. Each station is configured for receiving and decoding a timestamp in a beacon frame transmitted repeatedly from the access point. This is used to control the output signal of a station physical layer clock (12) which is then used as a clock source for an application layer time synchronisation protocol. This application layer time synchronisation protocol can then be used in the station to control an operating system clock (8) for regulating playback of media.

Abstract: A method and system for generating two or three dimensional computer graphics images using multisample antialiasing (MSAA) is provided, which enables memory bandwidth to be conserved. For each of one or more pixels it is determined whether all of a plurality of sample areas of that pixel are located within a particular primitive. For those pixels where it is determined that all the sample areas of that pixel are located within that primitive, a value is stored in a multisample memory for a smaller number of the sample areas of that pixel than the total number of the sample areas of that pixel and data is stored indicating that all the sample areas of that pixel are located within that primitive.

Abstract: Methods and image processing systems are provided for determining a dominant gradient orientation for a target region within an image. A plurality of gradient samples are determined for the target region, wherein each of the gradient samples represents a variation in pixel values within the target region. The gradient samples are converted into double-angle gradient vectors, and the double-angle gradient vectors are combined so as to determine a dominant gradient orientation for the target region.

Abstract: Apparatus for binning an input value into one of a plurality of bins which collectively represent a histogram of input values, each of the plurality of bins representing a corresponding range of input values, the apparatus comprising: an input for receiving an input value; a noise source configured to generate an error value according to a predetermined noise distribution; and a binning controller configured to mix the received input value with the error value so as to generate a modified input value and to allocate the modified input value to the bin corresponding to that modified input value.

Abstract: A pixel filter has a filter module that performs a first recursive filter operation in a first direction through a sequence of pixels to form a first filtered pixel value for each pixel, and performs a second recursive filter operation in a second direction through the sequence of pixels to form a second filtered pixel value for each pixel, the first and second recursive filter operations forming a respective filtered pixel value for a given pixel in dependence on the pixel value at that pixel and the filtered pixel value preceding that pixel in their respective direction of operation. The filtered pixel value of the preceding pixel is scaled by a measure of similarity between data associated with that pixel and its preceding pixel. Filter logic combines the first and second filtered pixel values formed by the first and second recursive filter operations to generate a filter output for the pixel, for each pixel of the sequence.

Abstract: A tessellation method uses tessellation factors defined for each vertex of a patch which may be a quad, a triangle or an isoline. The method is implemented in a computer graphics system and involves comparing the vertex tessellation factors to a threshold. If the vertex tessellation factors for either a left vertex or a right vertex, which define an edge of an initial patch, exceed the threshold, the edge is sub-divided by the addition of a new vertex which divides the edge into two parts and two new patches are formed. New vertex tessellation factors are calculated for each vertex in each of the newly formed patches, both of which include the newly added vertex. The method is then repeated for each of the newly formed patches until none of the vertex tessellation factors exceed the threshold.

Abstract: A method of performing safety-critical rendering at a graphics processing unit within a graphics processing system, the method comprising: receiving, at the graphics processing system, graphical data for safety-critical rendering at the graphics processing unit; scheduling at a safety controller, in accordance with a reset frequency, a plurality of resets of the graphics processing unit; rendering the graphical data at the graphics processing unit; and the safety controller causing the plurality of resets of the graphics processing unit to be performed commensurate with the reset frequency.

Abstract: Hierarchical acceleration structures with implicitly represented nodes are used for intersection testing in a ray tracing system. Nodes of the hierarchical acceleration structure each represents a region in a scene and are linked to form the hierarchical acceleration structure. Data is stored representing the hierarchical acceleration structure including data defining the regions represented by a plurality of the nodes of the hierarchical acceleration structure. At least one node of the hierarchical acceleration structure is an implicitly represented node, wherein data represented by an implicitly represented node is not explicitly included as part of the stored data but can be inferred from the stored data. Intersection testing in the ray tracing system is performed in which, based on conditions in the ray tracing system, a determination is made as to whether testing of one or more rays for intersection with a region represented by a particular node of a sub-tree is to be skipped.

Abstract: Conservative rasterization hardware comprises hardware logic arranged to perform an edge test calculation for each edge of a primitive and for two corners of each pixel in a microtile. The two corners that are used are selected based on the gradient of the edge and the edge test result for one corner is the inner coverage result and the edge test result for the other corner is the outer coverage result for the pixel. An overall outer coverage result for the pixel and the primitive is calculated by combining the outer coverage results for the pixel and each of the edges of the primitive in an AND gate. The overall inner coverage result for the pixel is calculated in a similar manner.

Abstract: Methods and tessellation modules for tessellating a patch to generate tessellated geometry data representing the tessellated patch. Received geometry data representing a patch is processed to identify tessellation factors of the patch. Based on the identified tessellation factors of the patch, tessellation instances to be used in tessellating the patch are determined. The tessellation instances are allocated amongst a plurality of tessellation pipelines that operate in parallel, wherein a respective set of one or more of the tessellation instances is allocated to each of the tessellation pipelines, and wherein each of the tessellation pipelines generates tessellated geometry data associated with the respective allocated set of one or more of the tessellation instances.

Abstract: A memory interface for interfacing between a memory bus addressable using a physical address space and a cache memory addressable using a virtual address space, the memory interface comprising: a memory management unit configured to maintain a mapping from the virtual address space to the physical address space; and a coherency manager comprising a reverse translation module configured to maintain a mapping from the physical address space to the virtual address space; wherein the memory interface is configured to: receive a memory read request from the cache memory, the memory read request being addressed in the virtual address space; translate the memory read request, at the memory management unit, to a translated memory read request addressed in the physical address space for transmission on the memory bus; receive a snoop request from the memory bus, the snoop request being addressed in the physical address space; and translate the snoop request, at the coherency manager, to a translated snoop request addr

Abstract: A computer-implemented method for generating a feature descriptor for a location in an image for use in performing descriptor matching in analysing the image, the method comprising determining a set of samples characterising a location in an image by sampling scale-space data representative of the image, the scale-space data comprising data representative of the image at a plurality of length scales; and generating a feature descriptor in dependence on the determined set of samples.

Abstract: Methods for converting an n-bit number into an m-bit number for situations where n>m and also for situations where n<m, where n and m are integers. The methods use truncation or bit replication followed by the calculation of an adjustment value which is applied to the replicated number.

Abstract: A hardware monitor arranged to detect livelock in a hardware design for an integrated circuit. The hardware monitor includes monitor and detection logic configured to detect when a particular state has occurred in an instantiation of the hardware design; and assertion evaluation logic configured to periodically evaluate one or more assertions that assert a formal property related to reoccurrence of the particular state in the instantiation of the hardware design to detect whether the instantiation of the hardware design is in a livelock comprising the predetermined state. The hardware monitor may be used by a formal verification tool to exhaustively verify that the instantiation of the hardware design cannot enter a livelock comprising the predetermined state.

Abstract: A synchronisation symbol detector that comprises two correlation modules and a comparison module. The first correlation module performs one or more correlations between the input signal and a down-converted version of the input signal and generates a first correlation metric from the one or more first correlations. The second correlation module performs one or more second correlations between the input signal and an up-converted version of the input signal and generates a second correlation metric from the one or more second correlations. The comparison module is configured to compare the first correlation metric and the second correlation metric and determine whether the input signal comprises a synchronisation symbol based on the comparison.

Abstract: A method of scheduling instructions within a parallel processing unit is described. The method comprises decoding, in an instruction decoder, an instruction in a scheduled task in an active state, and checking, by an instruction controller, if an ALU targeted by the decoded instruction is a primary instruction pipeline. If the targeted ALU is a primary instruction pipeline, a list associated with the primary instruction pipeline is checked to determine whether the scheduled task is already included in the list. If the scheduled task is already included in the list, the decoded instruction is sent to the primary instruction pipeline.

Abstract: A circuit for use in a processor includes a first processing channel having a first logic unit, a second processing channel having a second logic unit, and multiplexing circuitry. The multiplexing circuitry includes an input multiplexer arranged to switch between a first state in which an input of the first logic unit is coupled to an input line of the first processing channel, and a respective second state in which the input of the first logic unit is instead coupled to an input line of the second processing channel; and an output multiplexer arranged to switch between a first state in which an output line of the second processing channel is coupled to an output of the second logic unit, and a second state in which the output line of the second processing channel is instead coupled to an output of the first logic unit.

Abstract: A method of encoding data values where the data values are arranged into words, each word having a plurality of input values and one or more padding bits. A word is encoded by determining whether more than half of the bits in a portion of the word are ones, where the portion may be some or all of the bits of the input values in the word, and in response to determining that more than half of the bits in the portion are ones, inverting all the bits in the portion and setting a corresponding padding bit to a value to indicate the inversion.

Abstract: Implementations of blender hardware perform both domain shading and blending and whilst some vertices may not require blending, all vertices require domain shading. The blender hardware includes a cache and/or a content addressable memory and these data structures are used to reduce duplicate domain shading operations.

Abstract: A method of transmitting data in a media stream in accordance with a media streaming protocol includes generating data of a first type associated with a first type identifier in accordance with the protocol, encapsulating the generated data in a data structure defined by the protocol, the data structure including a type identifier field for specifying a type of data contained within the data structure, setting the type identifier field to a second type identifier different than the first type identifier, forming a packet comprising the first data structure, and transmitting the packet in the media stream.