Patents Assigned to Imagination Technologies
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Patent number: 11307862Abstract: A data processing system includes a processor operable to execute a program partitioned into a number of discrete instructions, the processor having multiple processing elements each capable of executing more than one instruction per cycle, and an interface configured to read a first program and, on detecting a branch operation by that program creating m number of branches each having a different sequence of instructions, combine an instruction from one of the branches with an instruction from at least one other branch so as to cause a processing element to execute the combined instructions during a single cycle.Type: GrantFiled: December 12, 2019Date of Patent: April 19, 2022Assignee: Imagination Technologies LimitedInventor: Jung-Wook Park
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Patent number: 11309907Abstract: Lossy methods and hardware for compressing data and the corresponding decompression methods and hardware are described. The lossy compression method comprises dividing a block of pixels into a number of sub-blocks and then analysing, for each sub-block, and selecting one of a candidate set of lossy compression modes. The analysis may, for example, be based on the alpha values for the pixels in the sub-block. In various examples, the candidate set of lossy compression modes comprises at least one mode that uses a fixed alpha channel value for all pixels in the sub-block and one or more modes that encode a variable alpha channel value.Type: GrantFiled: October 21, 2020Date of Patent: April 19, 2022Assignee: Imagination Technologies LimitedInventors: Simon Fenney, Linling Zhang
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Patent number: 11308683Abstract: Ray tracing systems and computer-implemented methods perform intersection testing on a bundle of rays with respect to a box. Silhouette edges of the box are identified from the perspective of the bundle of rays. For each of the identified silhouette edges, components of a vector providing a bound to the bundle of rays are obtained and it is determined whether the vector passes inside or outside of the silhouette edge. Results of determining, for each of the identified silhouette edges, whether the vector passes inside or outside of the silhouette edge, are used to determine an intersection testing result for the bundle of rays with respect to the box.Type: GrantFiled: June 29, 2020Date of Patent: April 19, 2022Assignee: Imagination Technologies LimitedInventors: Gregory Clark, Steven J. Clohset, Luke T. Peterson
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Patent number: 11302057Abstract: Systems can identify visible surfaces for pixels in an image (portion) to be rendered. A sampling pattern of ray directions is applied to the pixels, so that the sampling pattern of ray directions repeats, and with respect to any pixel, the same ray direction can be found in the same relative position, with respect to that pixel, as for other pixels. Rays are emitted from visible surfaces in the respective ray direction supplied from the sampling pattern. Ray intersections can cause shaders to execute and contribute results to a sample buffer. With respect to shading of a given pixel, ray results from a selected subset of the pixels are used; the subset is selected by identifying a set of pixels, collectively from which rays were traced for the ray directions in the pattern, and requiring that surfaces from which rays were traced for those pixels satisfy a similarity criteria.Type: GrantFiled: December 4, 2020Date of Patent: April 12, 2022Assignee: Imagination Technologies LimitedInventors: Gareth Morgan, Luke T. Peterson
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Patent number: 11295509Abstract: Ray tracing systems and computer-implemented methods perform intersection testing on a bundle of rays with respect to a box. A bundle of rays to be tested for intersection with a box is received, and a first bundle intersection test is performed to determine whether or not all of the rays of the bundle intersect the box, wherein if the first bundle intersection test determines that all of the rays of the bundle intersect the box, an intersection testing result for the bundle with respect to the box is that all of the rays of the bundle intersect the box. If the first bundle intersection test does not determine that all of the rays of the bundle intersect the box, a second bundle intersection test is performed, which determines whether or not all of the rays of the bundle miss the box, the result of which is used to determine the intersection testing result for the bundle with respect to the box.Type: GrantFiled: June 29, 2020Date of Patent: April 5, 2022Assignee: Imagination Technologies LimitedInventors: Gregory Clark, Steven J. Clohset, Luke T. Peterson
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Patent number: 11295485Abstract: A binary logic circuit for performing an interpolation calculation between two endpoint values E0 and E1 using a weighting index i for generating an interpolated result P, the values E0 and E1 being formed from Adaptive Scalable Texture Compression (ASTC) low-dynamic range (LDR) colour endpoint values C0 and C1 respectively, the circuit comprising: an interpolation unit configured to perform an interpolation between the colour endpoint values C0 and C1 using the weighting index i to generate a first intermediate interpolated result C2; and combinational logic circuitry configured to receive the interpolated result C2 and to perform one or more logical processing operations to calculate the interpolated result P according to the equation P=?((C2<<8)+C2+32)/64? when the interpolated result is not to be compatible with an sRGB colour space, and according to the equation P=?((C2<<8)+128.64+32)/64? when the interpolated result is to be compatible with an sRGB colour space.Type: GrantFiled: December 20, 2019Date of Patent: April 5, 2022Assignee: Imagination Technologies LimitedInventor: Kenneth Rovers
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Patent number: 11294634Abstract: A binary logic circuit for determining the ratio x/d where x is a variable integer input, the binary logic circuit comprising: a logarithmic tree of modulo units each configured to calculate x[a: b] mod d for respective block positions a and b in x where b>a with the numbering of block positions increasing from the most significant bit of x up to the least significant bit of x, the modulo units being arranged such that a subset of M?1 modulo units of the logarithmic tree provide x[0: m] mod d for all m?{1, M}, and, on the basis that any given modulo unit introduces a delay of 1: all of the modulo units are arranged in the logarithmic tree within a delay envelope of ?log2 M?; and more than M?2u of the subset of modulo units are arranged at the maximal delay of ?log2 M?, where 2u is the power of 2 immediately smaller than M.Type: GrantFiled: August 22, 2019Date of Patent: April 5, 2022Assignee: Imagination Technologies LimitedInventors: Jonas Källén, Sam Elliott
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Patent number: 11294625Abstract: Methods and systems for determining whether an infinitely precise result of a reciprocal square root operation performed on an input floating point number is greater than a particular number in a first floating point precision. The method includes calculating the square of the particular number in a second lower floating point precision; calculating an error in the calculated square due to the second floating point precision; calculating a first delta value in the first floating point precision by calculating the square multiplied by the input floating point number less one; calculating a second delta value by calculating the error multiplied by the input floating point number plus the first delta value; and outputting an indication of whether the infinitely precise result of the reciprocal square root operation is greater than the particular number based on the second delta term.Type: GrantFiled: October 14, 2016Date of Patent: April 5, 2022Assignee: Imagination Technologies LimitedInventors: Casper Van Benthem, Sam Elliott
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Patent number: 11295524Abstract: A graphics processing system includes a tiling unit configured to tile a first view of a scene into a plurality of tiles, a processing unit configured to identify a first subset of the tiles that are associated with regions of the scene that are viewable in a second view, and a rendering unit configured to render to a render target each of the identified tiles.Type: GrantFiled: December 23, 2020Date of Patent: April 5, 2022Assignee: Imagination Technologies LimitedInventors: Simon Fenney, Michael Worcester, Stuart Smith
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Patent number: 11287843Abstract: A first device operates synchronously with a second device, and includes a hardware clock having an adjustable clock frequency and a software clock configured to derive time in dependence on the hardware clock. A controller determines a synchronisation error between the software clock and a clock of the second device, and adjusts the clock frequency of the hardware clock in dependence on the synchronisation error so as to synchronise the hardware clock to a hardware clock of the second device.Type: GrantFiled: September 21, 2020Date of Patent: March 29, 2022Assignee: Imagination Technologies LimitedInventors: Martin Woodhead, Arnold Mark Bilstad
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Patent number: 11288145Abstract: A graphics processing system includes a plurality of processing units for processing tasks, each processing unit being configured to process a task independently from any other processing unit of the plurality of processing units; a check unit operable to form a signature which is characteristic of an output of a processing unit on processing a task; and a fault detection unit operable to compare signatures formed at the check unit; wherein the graphics processing system is configured to process each task of a first type first and second times at the plurality of processing units so as to, respectively, generate first and second processed outputs, wherein the check unit is configured to form first and second signatures which are characteristic of, respectively, the first and second processed outputs, and wherein the fault detection unit is configured to compare the first and second signatures and raise a fault signal if the first and second signatures do not match.Type: GrantFiled: December 4, 2019Date of Patent: March 29, 2022Assignee: Imagination Technologies LimitedInventors: Damien McNamara, Jamie Broome, Ian King, Wei Shao, Mario Sopena Novales, Dilip Bansal
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Patent number: 11289049Abstract: A colour processor for mapping an image from source to destination colour gamuts includes an input for receiving a source image having a plurality of source colour points expressed according to the source gamut; a colour characterizer configured to, for each source colour point in the source image, determine a position of intersection of a curve with the boundary of the destination gamut; and a gamut mapper configured to, for each source colour point in the source image: if the source colour point lies inside the destination gamut, apply a first translation factor to translate the source colour point to a destination colour point within a first range of values; or if the source colour point lies outside the destination gamut, apply a second translation factor, different than the first translation factor, to translate the source colour point to a destination colour point within a second range of values.Type: GrantFiled: July 9, 2020Date of Patent: March 29, 2022Assignee: Imagination Technologies LimitedInventor: Paolo Fazzini
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Patent number: 11288855Abstract: Rendering system combines point sampling and volume sampling operations to produce rendering outputs. For example, to determine color information for a surface location in a 3-D scene, one or more point sampling operations are conducted in a volume around the surface location, and one or more sampling operations of volumetric light transport data are performed farther from the surface location. A transition zone between point sampling and volume sampling can be provided, in which both point and volume sampling operations are conducted. Data obtained from point and volume sampling operations can be blended in determining color information for the surface location. For example, point samples are obtained by tracing a ray for each point sample, to identify an intersection between another surface and the ray, to be shaded, and volume samples are obtained from a nested 3-D grids of volume elements expressing light transport data at different levels of granularity.Type: GrantFiled: September 5, 2019Date of Patent: March 29, 2022Assignee: Imagination Technologies LimitedInventors: Cuneyt Ozdas, Luke Tilman Peterson
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Patent number: 11282216Abstract: A reduced noise image can be formed from a set of images. One of the images of the set can be selected to be a reference image and other images of the set are transformed such that they are better aligned with the reference image. A measure of the alignment of each image with the reference image is determined. At least some of the transformed images can then be combined using weights which depend on the alignment of the transformed image with the reference image to thereby form the reduced noise image. By weighting the images according to their alignment with the reference image the effects of misalignment between the images in the combined image are reduced. Furthermore, motion correction may be applied to the reduced noise image.Type: GrantFiled: May 4, 2020Date of Patent: March 22, 2022Assignee: Imagination Technologies LimitedInventors: Marc Vivet, Paul Brasnett
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Patent number: 11284090Abstract: Methods and apparatus for compressing image data are described along with corresponding methods and apparatus for decompressing the compressed image data. An encoder unit, which generates the compressed image data, comprises an input arranged to receive a first image and a second image, wherein the second image is twice the width and height of the first image, a prediction generator arranged to generate a prediction texture from the first image using an adaptive interpolator, a difference texture generator arranged to generate a difference texture from the prediction texture and the second image and in encoder unit arranged to encode the difference texture.Type: GrantFiled: April 22, 2020Date of Patent: March 22, 2022Assignee: Imagination Technologies LimitedInventor: Rostam King
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Patent number: 11282262Abstract: Ray tracing systems have computation units (“RACs”) adapted to perform ray tracing operations (e.g. intersection testing). There are multiple RACs. A centralized packet unit controls the allocation and testing of rays by the RACs. This allows RACs to be implemented without Content Addressable Memories (CAMs) which are expensive to implement, but the functionality of CAMs can still be achieved by implemented them in the centralized controller.Type: GrantFiled: December 18, 2020Date of Patent: March 22, 2022Assignee: Imagination Technologies LimitedInventors: Joseph M. Richards, Luke T. Peterson, Steven J. Clohset
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Patent number: 11282162Abstract: A method and system for generating and shading a computer graphics image in a tile based computer graphics system is provided. Geometry data is supplied and a plurality of primitives are derived from the geometry data. One or more modified primitives are then derived from at least one of the plurality of primitives. For each of a plurality of tiles, an object list is derived including data identifying the primitive from which each modified primitive located at least partially within that tile is derived. Alternatively, the object list may include data identifying each modified primitive located at least partially within that tile. Each tile is then shaded for display using its respective object list.Type: GrantFiled: October 6, 2020Date of Patent: March 22, 2022Assignee: Imagination Technologies LimitedInventors: Steven J. Fishwick, John W. Howson
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Patent number: 11276233Abstract: A graphics system has a rendering space divided into a plurality of rectangular areas, each being sub-divided into a plurality of smaller rectangular areas of a plurality of pixels. Data is received representing a tiled set of polygons to be rendered in a selected one of the rectangular areas. For each polygon, a determination is made whether that polygon is located at least partially inside a selected one of the smaller rectangular areas in the selected rectangular area. If so, which pixels of the plurality of pixels in the selected smaller rectangular area are inside the polygon are identified. Or, if that polygon is not located at least partially inside the selected smaller rectangular area, no further processing of the polygon is performed at one or more of the plurality of pixels in the smaller rectangular area.Type: GrantFiled: October 21, 2020Date of Patent: March 15, 2022Assignee: Imagination Technologies LimitedInventors: Piers Barber, Simon Fenney
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Patent number: 11276212Abstract: Conservative rasterization hardware comprises hardware logic arranged to perform an edge test calculation for each edge of a primitive and for each corner of each pixel in a microtile. Outer coverage results are determined, for a particular pixel and edge, by combining the edge test results for the four corners of the pixel and the particular edge in an OR gate. Inner coverage results are determined, for a particular pixel and edge, by combining the edge test results for the four corners of the pixel and the particular edge in an AND gate. An overall outer coverage result for the pixel and the primitive is calculated by combining the outer coverage results for the pixel and each of the edges of the primitive in an AND gate. The overall inner coverage result for the pixel is calculated in a similar manner.Type: GrantFiled: November 4, 2020Date of Patent: March 15, 2022Assignee: Imagination Technologies LimitedInventor: Casper Van Benthem
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Patent number: 11276222Abstract: A rendering optimisation identifies a draw call within a current render (which may be the first draw call in the render or a subsequent draw call in the render) and analyses a last shader in the series of shaders used by the draw call to determine whether the last shader samples from the one or more buffers at coordinates matching a current fragment location. If this determination is positive, the method further recompiles the last shader to replace an instruction that reads data from one of the one or more buffers at coordinates matching a current fragment location with an instruction that reads from the one or more buffers at coordinates stored in on-chip registers.Type: GrantFiled: May 31, 2020Date of Patent: March 15, 2022Assignee: Imagination Technologies LimitedInventor: James Glanville