Abstract: Time stamp replication within wireless networks is described. In an embodiment, a wireless station receives an input time stamp and uses this input time stamp to generate an output time stamp. The wireless station transmits the output time stamp to wireless stations in one of a number of groups which make up the wireless network. The output time stamp is generated to compensate for delays between receiving the input time stamp and transmitting the output time stamp such that output time stamp which is transmitted at a time T corresponds to the value that the input time stamp would have had if it had been received at time T (and not at a time earlier than T). This may, therefore, reduce or eliminate independent time stamp errors and jitter caused by multiple disparate systems and processes.

Abstract: Anisotropic texture filtering applies a texture at a sampling point in screen space. Calculated texture-filter parameters configure a filter to perform filtering of the texture for the sampling point. The texture for the sampling point is filtered using a filtering kernel having a footprint in texture space determined by the texture-filter parameters. Texture-filter parameters are calculated by generating a first and a second pair of screen-space basis vectors being rotated relative to each other. First and second pairs of texture-space basis vectors are calculated that correspond to the first and second pairs of screen-space basis vectors transformed to texture space under a local approximation of a mapping between screen space and texture space. An angular displacement is determined between a selected pair of the first and second pairs of screen-space basis vectors and screen-space principal axes of a local approximation of the mapping that indicate the maximum and minimum scale factors of the mapping.

Abstract: An apparatus and a method for generating 3-dimensional computer graphic images. The image is first sub-divided into a plurality of rectangular areas. A display list memory is loaded with object data for each rectangular area. The image and shading data for each picture element of each rectangular area are derived from the object data in the image synthesis processor and a texturizing and shading processor. A depth range generator derives a depth range for each rectangular area from the object data as the imaging and shading data is derived. This is compared with the depth of each new object to be provided to the image synthesis processor and the object may be prevented from being provided to the image synthesis processor independence on the result of the comparison.

Abstract: Methods and primitive block generators for generating primitive blocks in a graphics processing system. The methods comprise: receiving transformed position data for a current primitive, the transformed position data indicating a position of the current primitive in rendering space; determining a distance between the position of the current primitive and a position of a current primitive block based on the transformed position data for the current primitive; determining whether to add the current primitive to the current primitive block based on the distance and a fullness of the current primitive block; in response to determining that the current primitive is to be added to the current primitive block, adding the current primitive to the current primitive block; and in response to determining that the current primitive is not to be added to the current primitive block, flushing the current primitive block and adding the current primitive to a new current primitive block.

Abstract: Tile based interleaving and de-interleaving of row-column interleaved data is described. In one example, the de-interleaving is divided into two memory transfer stages, the first from an on-chip memory to a DRAM and the second from the DRAM to an on-chip memory. Each stage operates on part of a row-column interleaved block of data and re-orders the data items, such that the output of the second stage comprises de-interleaved data. In the first stage, data items are read from the on-chip memory according to a non-linear sequence of memory read addresses and written to the DRAM. In the second stage, data items are read from the DRAM according to bursts of linear address sequences which make efficient use of the DRAM interface and written back to on-chip memory according to a non-linear sequence of memory write addresses.

Abstract: Aspects comprise systems implementing 3-D graphics processing functionality in a multiprocessing system. Control flow structures are used in scheduling instances of computation in the multiporcessing system, where different points in the control flow structure serve as points where deferral of some instances of computation can be performed in favor of scheduling other instances of computation. In some examples, the control flow structure identifies particular tasks, such as intersection testing of a particular portion of an acceleration structure, and a particular element of shading code. In some examples, the aspects are used in 3-D graphics processing systems that can perform ray tracing based rendering.

Abstract: A method of scheduling tasks within a GPU or other highly parallel processing unit is described which is both age-aware and wakeup event driven. Tasks which are received are added to an age-based task queue. Wakeup event bits for task types, or combinations of task types and data groups, are set in response to completion of a task dependency and these wakeup event bits are used to select an oldest task from the queue that satisfies predefined criteria.

Abstract: Methods and parallel processing units for avoiding inter-pipeline data hazards wherein inter-pipeline data hazards are identified at compile time. For each identified inter-pipeline data hazard the primary instruction and secondary instruction(s) thereof are identified as such and are linked by a counter which is used to track that inter-pipeline data hazard. Then when a primary instruction is output by the instruction decoder for execution the value of the counter associated therewith is adjusted (e.g. incremented) to indicate that there is hazard related to the primary instruction, and when primary instruction has been resolved by one of multiple parallel processing pipelines the value of the counter associated therewith is adjusted (e.g. decremented) to indicate that the hazard related to the primary instruction has been resolved.

Abstract: A texture filtering unit includes a datapath block and a control block. The datapath block includes one or more parallel computation pipelines, each containing at least one hardware logic component configured to receive a plurality of inputs and generate an output value as part of a texture filtering operation. The control block includes a plurality of sequencers and an arbiter. Each sequencer executes a micro-program that defines a sequence of operations to be performed by the one or more pipelines in the datapath block as part of a texture filtering operation and the arbiter controls access, by the sequencers, to the one or more pipelines in the datapath based on predefined prioritization rules.

Abstract: A method of activating scheduling instructions within a parallel processing unit includes checking if an ALU targeted by a decoded instruction is full by checking a value of an ALU work fullness counter stored in the instruction controller and associated with the targeted ALU. If the targeted ALU is not full, the decoded instruction is sent to the targeted ALU for execution and the ALU work fullness counter associated with the targeted ALU is updated. If, however, the targeted ALU is full, a scheduler is triggered to de-activate the scheduled task by changing the scheduled task from the active state to a non-active state. When an ALU changes from being full to not being full, the scheduler is triggered to re-activate an oldest scheduled task waiting for the ALU by removing the oldest scheduled task from the non-active state.

Abstract: Methods and system for converting a plurality of weights of a filter of a Deep Neural Network (DNN) in a first number format to a second number format, the second number format having less precision than the first number format, to enable the DNN to be implemented in hardware logic.

Abstract: A SIMD processing unit processes a plurality of tasks which each include up to a predetermined maximum number of work items. The work items of a task are arranged for executing a common sequence of instructions on respective data items. The data items are arranged into blocks, with some of the blocks including at least one invalid data item. Work items which relate to invalid data items are invalid work items. The SIMD processing unit comprises a group of processing lanes configured to execute instructions of work items of a particular task over a plurality of processing cycles. A control module assembles work items into the tasks based on the validity of the work items, so that invalid work items of the particular task are temporally aligned across the processing lanes. In this way the number of wasted processing slots due to invalid work items may be reduced.

Abstract: Hardware for implementing a Deep Neural Network (DNN) having a convolution layer, the hardware comprising a plurality of convolution engines each configured to perform convolution operations by applying filters to data windows, each filter comprising a set of weights for combination with respective data values of a data window; and one or more weight buffers accessible to each of the plurality of convolution engines over an interconnect, each weight buffer being configured to provide weights of one or more filters to any of the plurality of convolution engines; wherein each of the convolution engines comprises control logic configured to request weights of a filter from the weight buffers using an identifier of that filter.

Abstract: A method and system is provided for culling hidden objects in a tile-based graphics system before they are indicated in a display list for a tile. A rendering space is divided into a plurality of regions which may for example be a plurality of tiles or a plurality of areas into which one or more tiles are divided. Depth thresholds for the regions, which are used to identify hidden objects for culling, are updated when an object entirely covers a region and in dependence on a comparison between a depth value for the object and the depth threshold for the region. For example, if the depth threshold is a maximum depth threshold, the depth threshold may be updated if an object entirely covers the tile and the maximum depth value of the object is less than the maximum depth threshold.

Abstract: Channel state information (CSI) scaling modules for use in a demodulator configured to demodulate a signal received over a transmission channel, the demodulator comprising a soft decision error corrector (e.g. LDPC decoder) configured to decode data carried on data symbols of the received signal based on CSI values. The CSI scaling module is configured to monitor the performance of the soft decision error corrector and in response to determining the performance of the soft decision error corrector is below a predetermined level, dynamically select a new CSI scaling factor based on the performance of the soft decision error corrector.

Abstract: An interlaced video signal can include content of different types, such as interlaced content and progressive content. The progressive content may have different cadences according to the ratio between the frame rate of the progressive content and the field rate of the interlaced video signal. Cadence analysis is performed to identify the cadence of the video signal and/or to determine field pairings when progressive content is included. As described herein, motion information (e.g. motion vectors) for blocks of fields of a video signal can be used for the cadence analysis. The use of motion information provides a robust method of performing cadence analysis.

Abstract: A graphics processing system performs hidden surface removal and texturing/shading on fragments of primitives. The system includes a primary depth buffer (PDB) for storing depth values of resolved fragments, and a secondary depth buffer (SDB) for storing depth values of unresolved fragments. Incoming fragments are depth tested against depth values from either the PDB or the SDB. When a fragment passes a depth test, its depth value is stored in the PDB if it is a resolved fragment (e.g. if it is opaque or translucent), and its depth value is stored in the SDB if it is an unresolved fragment (e.g. if it is a punch through fragment). This provides more opportunities for subsequent opaque objects to overwrite punch through fragments which passed a depth test, thereby reducing unnecessary processing and time which may be spent on fragments which ultimately will not contribute to the final rendered image.

Abstract: Apparatus for evaluating a mathematical function for a received input value includes a polynomial block configured to identify a domain interval containing the received input value over which the mathematical function can be evaluated, the mathematical function over the identified interval being approximated by a polynomial function; and evaluate the polynomial function for the received input value using a set of one or more stored values representing the polynomial function over the identified interval to calculate a first evaluation of the mathematical function for the received input value; and a CORDIC block for performing a CORDIC algorithm, configured to initialise the CORDIC algorithm using the first evaluation of the mathematical function for the received input value calculated by the polynomial block; and implement the CORDIC algorithm to calculate a refined evaluation of the mathematical function for the received input value.

Abstract: A graphics processing system has a rendering space which is divided into tiles. Primitives within the tiles are processed to perform hidden surface removal and to apply texturing to the primitives. The graphics processing system includes a plurality of depth buffers, thereby allowing a processing module to process primitives of one tile by accessing one of the depth buffers while primitive identifiers of another, partially processed tile are stored in another one of the depth buffers. This allows the graphics processing system to have “multiple tiles in flight”, which can increase the efficiency of the graphics processing system.

Abstract: Methods and coarse depth test logic perform coarse depth testing in a graphics processing system in which a rendering space is divided into a plurality of tiles. A depth range for a tile is obtained, which identifies a depth range based on primitives previously processed for the tile. A determination is made based on the depth range for the tile as to whether all or a portion of a primitive is hidden in the tile. If at least a portion of the primitive is not hidden in the tile, a determination is as to whether the primitive, or one or more primitive fragments thereof has better depth than the primitives previously processed for the tile according to a depth compare mode. If so, the primitive or the primitive fragment is identified as not requiring a read of a depth buffer to perform full resolution depth testing, such that a determination that at least a portion of the primitive is hidden in the tile causes full resolution depth testing not to be performed on at least that portion of the primitive.