Patents Assigned to Imagination Technologies
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Patent number: 11263811Abstract: A tessellation method uses vertex tessellation factors. For a quad patch, the method involves comparing the vertex tessellation factors for each vertex of the quad patch to a threshold value and if none exceed the threshold, the quad is sub-divided into two or four triangles. If at least one of the four vertex tessellation factors exceeds the threshold, a recursive or iterative method is used which considers each vertex of the quad patch and determines how to further tessellate the patch dependent upon the value of the vertex tessellation factor of the selected vertex or dependent upon values of the vertex tessellation factors of the selected vertex and a neighbor vertex. A similar method is described for a triangle patch.Type: GrantFiled: June 4, 2020Date of Patent: March 1, 2022Assignee: Imagination Technologies LimitedInventors: Simon Fenney, Vasiliki Simaiaki
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Patent number: 11263798Abstract: A graphics processing unit having multiple groups of processor cores for rendering graphics data for allocated tiles and outputting the processed data to regions of a memory resource. Scheduling logic allocates sets of tiles to the groups of processor cores to perform a first render, and at a time when at least one of the groups has not completed processing its allocated sets of one or more tiles as part of the first render, allocates at least one set of tiles for a second render to one of the other groups of processor cores for processing. Progress indication logic indicates progress of the first render, indicating regions of the memory resource for which processing for the first render has been completed. Progress check logic checks the progress indication in response to a request for access to a region of the memory resource as part of the second render and enables access that region of the resource in response to an indication that processing for the first render has been completed for that region.Type: GrantFiled: May 31, 2020Date of Patent: March 1, 2022Assignee: Imagination Technologies LimitedInventors: John Howson, Steven Fishwick
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Patent number: 11263288Abstract: An aspect includes an apparatus for evaluating a mathematical function at an input value. The apparatus includes a selector for selecting a mathematical function, an input for a value at which to evaluate the function, an identifier for identifying an interval containing the input value. The interval is described by at least one polynomial function. At least one control point representing the polynomial function is retrieved from at least one look up table, and the polynomial function can be derived from the control points. The function is evaluated at the input value and an output of the evaluation is used as a value of the function at that input value.Type: GrantFiled: November 9, 2012Date of Patent: March 1, 2022Assignee: Imagination Technologies LimitedInventor: Simon Fenney
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Patent number: 11258457Abstract: A method of data compression in which the total size of the compressed data is determined and based on that determination, the bit depth of the input data may be reduced before the data is compressed. The bit depth that is used may be determined by comparing the calculated total size to one or more pre-defined threshold values to generate a mapping parameter. The mapping parameter is then input to a remapping element that is arranged to perform the conversion of the input data and then output the converted data to a data compression element. The value of the mapping parameter may be encoded into the compressed data so that it can be extracted and used when subsequently decompressing the data.Type: GrantFiled: September 14, 2020Date of Patent: February 22, 2022Assignee: Imagination Technologies LimitedInventors: Peter Malcolm Lacey, Simon Fenney
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Patent number: 11257181Abstract: In tile-based graphics processing systems, a tiling unit determines which tiles of a rendering space a primitive is in, such that the primitives in a tile can be rendered. Rather than performing tiling calculations for each tile in a bounding box for a primitive, tiling tests can be performed for a subset of the tiles. Then the results of the tiling tests for the subset of tiles can be used to determine whether the primitive is in other tiles which are located within a region bounded by two or more of the tiles of the subset. In this way the tiling process can be implemented without performing tiling calculations for all of the tiles in the bounding box for a primitive. Reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system (in terms of speed and power consumption) for rendering a primitive.Type: GrantFiled: July 15, 2020Date of Patent: February 22, 2022Assignee: Imagination Technologies LimitedInventor: Xile Yang
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Patent number: 11257271Abstract: In an aspect, an update unit can evaluate condition(s) in an update request and update one or more memory locations based on the condition evaluation. The update unit can operate atomically to determine whether to effect the update and to make the update. Updates can include one or more of incrementing and swapping values. An update request may specify one of a pre-determined set of update types. Some update types may be conditional and others unconditional. The update unit can be coupled to receive update requests from a plurality of computation units. The computation units may not have privileges to directly generate write requests to be effected on at least some of the locations in memory. The computation units can be fixed function circuitry operating on inputs received from programmable computation elements. The update unit may include a buffer to hold received update requests.Type: GrantFiled: September 26, 2016Date of Patent: February 22, 2022Assignee: Imagination Technologies LimitedInventors: Steven J. Clohset, Jason R. Redgrave, Luke T. Peterson
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Patent number: 11250192Abstract: A hardware monitor arranged to detect out-of-bounds violations in a hardware design for an electronic device. The hardware monitors include monitor and detection logic configured to monitor the current operating state of an instantiation of the hardware design and detect when the instantiation of the hardware design implements a fetch of an instruction from memory; and assertion evaluation logic configured to evaluate one or more assertions that assert a formal property that compares the memory address of the fetched instruction to an allowable memory address range associated with the current operating state of the instantiation of the hardware design to determine whether there has been an out-of-bounds violation. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design does not cause an instruction to be fetched from an out-of-bounds address.Type: GrantFiled: February 5, 2021Date of Patent: February 15, 2022Assignee: Imagination Technologies LimitedInventors: Ashish Darbari, Iain Singleton
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Patent number: 11250927Abstract: Hardware monitors which can be used by a formal verification tool to exhaustively verify a hardware design for a memory unit. The hardware monitors include detection logic to monitor one or more control signals and/or data signals of an instantiation of the memory unit to detect symbolic writes and symbolic reads. In some examples a symbolic write is a write of symbolic data to a symbolic address; and in other examples a symbolic write is a write of any data to a symbolic address. A symbolic read is a read of the symbolic address. The hardware monitors also include assertion verification logic that verifies an assertion that read data corresponding to a symbolic reads matches write data associated with one or more symbolic writes preceding the read.Type: GrantFiled: February 17, 2020Date of Patent: February 15, 2022Assignee: Imagination Technologies LimitedInventors: Ashish Darbari, Iain Singleton
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Patent number: 11249925Abstract: Apparatus identifies a set of M output memory addresses from a larger set of N input memory addresses containing at least one non-unique memory address. A comparator block performs comparisons of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresses from the set of input addresses, where each address in the subset identified by the binary classification dataset is unique within that subset. Combination logic units receive a predetermined selection of bits of the binary classification dataset and sort its received predetermined selection of bits into an intermediary binary string in which the bits are ordered into a first group identifying addresses belonging to the identified subset, and a second group identifying addresses not belonging to the identified subset.Type: GrantFiled: March 13, 2020Date of Patent: February 15, 2022Assignee: Imagination Technologies LimitedInventors: Luca Iuliano, Simon Nield, Thomas Rose
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Patent number: 11244498Abstract: A tiling unit assigning primitives to tiles in a graphics processing system which has a rendering space subdivided into a plurality of tiles. Each tile can comprise one or more polygonal region. Mesh logic of the tiling unit can determine that a plurality of primitives form a mesh and can determine whether the mesh entirely covers a region. If the mesh entirely covers the region then a depth threshold for the region can be updated so that subsequent primitives which lie behind the depth threshold are culled (i.e. not included in the display list for a tile). This helps to reduce the number of primitive IDs included in a display list for a tile which reduces the amount of memory used by the display list and reduces the number of primitives which a hidden surface removal (HSR) module needs to fetch to perform HSR on the tile.Type: GrantFiled: May 28, 2020Date of Patent: February 8, 2022Assignee: Imagination Technologies LimitedInventor: Xile Yang
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Patent number: 11244421Abstract: Memories and methods for storing untransformed primitive blocks of variable size in a memory structure of a graphics processing system, the untransformed primitive blocks having been generated by geometry processing logic of the graphics processing system. The method includes: storing an untransformed primitive block in the memory structure, and increasing, by a predetermined amount, a current total amount of memory allocated for storing untransformed primitive blocks; determining an unused amount of the current total amount of memory allocated for storing untransformed primitive blocks; receiving a new untransformed primitive block for storing in the memory structure, and determining whether a size of the new untransformed primitive block is less than or equal to the unused amount; and if it is determined that the size of the new untransformed primitive block is less than or equal to the unused amount, storing the new untransformed primitive block in the memory structure.Type: GrantFiled: January 29, 2020Date of Patent: February 8, 2022Assignee: Imagination Technologies LimitedInventor: Robert Brigg
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Patent number: 11244432Abstract: Image processing methods and systems apply filtering operations to images, wherein the filtering operations use filter costs which are based on image gradients in the images. In this way, image data is filtered for image regions in dependence upon the image gradients for the image regions. This may be useful for different scenarios such as when combining images to form a High Dynamic Range (HDR) image. The filtering operations may be used as part of a connectivity unit which determines connected image regions, and/or the filtering operations may be used as part of a blending unit which blends two or more images together to form a blended image.Type: GrantFiled: January 23, 2020Date of Patent: February 8, 2022Assignee: Imagination Technologies LimitedInventor: Ruan Lakemond
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Patent number: 11240406Abstract: There is provided a method and apparatus for motion estimation in a sequence of video images. The method comprises a) subdividing each field or frame of a sequence of video images into a plurality of blocks, b) assigning to each block in each video field or frame a respective set of candidate motion vectors, c) determining for each block in a current video field or frame, which of its respective candidate motion vectors produces a best match to a block in a previous video field or frame, d) forming a motion vector field for the current video field or frame using the thus determined best match vectors for each block, and e) forming a further motion vector field by storing a candidate motion vector derived from the best match vector at a block location offset by a distance derived from the candidate motion vector. Finally, steps a) to e) are repeated for a video field or frame following the current video field or frame.Type: GrantFiled: August 11, 2015Date of Patent: February 1, 2022Assignee: Imagination Technologies LimitedInventors: Steven John Fishwick, Stephen Morphet
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Patent number: 11238638Abstract: A graphics processing hardware pipeline is arranged to perform an edge test or a depth calculation. Each hardware arrangement includes a microtile component hardware element, multiple pixel component hardware elements, one or more subsample component hardware elements and a final addition and comparison unit. The microtile component hardware element calculates a first output using a sum-of-products and coordinates of a microtile within a tile in the rendering space. Each pixel component hardware element calculates a different second output using the sum-of-products and coordinates for different pixels defined relative to an origin of the microtile. The subsample component hardware element calculates a third output using the sum-of-products and coordinates for a subsample position defined relative to an origin of a pixel.Type: GrantFiled: August 21, 2020Date of Patent: February 1, 2022Assignee: Imagination Technologies LimitedInventor: Casper Van Benthem
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Patent number: 11232634Abstract: A method and apparatus for rendering a computer-generated image using a stencil buffer is described. The method divides an arbitrary closed polygonal contour into first and higher level primitives, where first level primitives correspond to contiguous vertices in the arbitrary closed polygonal contour and higher level primitives correspond to the end vertices of consecutive primitives of the immediately preceding primitive level. The method reduces the level of overdraw when rendering the arbitrary polygonal contour using a stencil buffer compared to other image space methods. A method of producing the primitives in an interleaved order, with second and higher level primitives being produced before the final first level primitives of the contour, is described which improves cache hit rate by reusing more vertices between primitives as they are produced.Type: GrantFiled: July 21, 2020Date of Patent: January 25, 2022Assignee: Imagination Technologies LimitedInventor: Simon Fenney
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Patent number: 11228388Abstract: Time stamp replication within wireless networks is described. In an embodiment, a wireless station receives an input time stamp and uses this input time stamp to generate an output time stamp. The wireless station transmits the output time stamp to wireless stations in one of a number of groups which make up the wireless network. The output time stamp is generated to compensate for delays between receiving the input time stamp and transmitting the output time stamp such that output time stamp which is transmitted at a time T corresponds to the value that the input time stamp would have had if it had been received at time T (and not at a time earlier than T). This may, therefore, reduce or eliminate independent time stamp errors and jitter caused by multiple disparate systems and processes.Type: GrantFiled: June 18, 2020Date of Patent: January 18, 2022Assignee: Imagination Technologies LimitedInventor: Ian Knowles
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Patent number: 11227362Abstract: Aspects include a multistage collector to receive outputs from plural processing elements. Processing elements may comprise (each or collectively) a plurality of clusters, with one or more ALUs that may perform SIMD operations on a data vector and produce outputs according to the instruction stream being used to configure the ALU(s). The multistage collector includes substituent components each with at least one input queue, a memory, a packing unit, and an output queue; these components can be sized to process groups of input elements of a given size, and can have multiple input queues and a single output queue. Some components couple to receive outputs from the ALUs and others receive outputs from other components. Ultimately, the multistage collector can output groupings of input elements. Each grouping of elements (e.g., at input queues, or stored in the memories of component) can be formed based on matching of index elements.Type: GrantFiled: September 4, 2020Date of Patent: January 18, 2022Assignee: Imagination Technologies LimitedInventors: James Alexander McCombe, Steven John Clohset, Jason Rupert Redgrave, Luke Tilman Peterson
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Patent number: 11217008Abstract: An apparatus and a method for generating 3-dimensional computer graphic images. The image is first sub-divided into a plurality of rectangular areas. A display list memory is loaded with object data for each rectangular area. The image and shading data for each picture element of each rectangular area are derived from the object data in the image synthesis processor and a texturizing and shading processor. A depth range generator derives a depth range for each rectangular area from the object data as the imaging and shading data is derived. This is compared with the depth of each new object to be provided to the image synthesis processor and the object may be prevented from being provided to the image synthesis processor independence on the result of the comparison.Type: GrantFiled: February 8, 2018Date of Patent: January 4, 2022Assignee: Imagination Technologies LimitedInventor: Stephen Morphet
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Patent number: 11217007Abstract: Methods and primitive block generators for generating primitive blocks in a graphics processing system. The methods comprise: receiving transformed position data for a current primitive, the transformed position data indicating a position of the current primitive in rendering space; determining a distance between the position of the current primitive and a position of a current primitive block based on the transformed position data for the current primitive; determining whether to add the current primitive to the current primitive block based on the distance and a fullness of the current primitive block; in response to determining that the current primitive is to be added to the current primitive block, adding the current primitive to the current primitive block; and in response to determining that the current primitive is not to be added to the current primitive block, flushing the current primitive block and adding the current primitive to a new current primitive block.Type: GrantFiled: December 21, 2019Date of Patent: January 4, 2022Assignee: Imagination Technologies LimitedInventors: Xile Yang, Robert Brigg, John W. Howson
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Patent number: 11216990Abstract: Anisotropic texture filtering applies a texture at a sampling point in screen space. Calculated texture-filter parameters configure a filter to perform filtering of the texture for the sampling point. The texture for the sampling point is filtered using a filtering kernel having a footprint in texture space determined by the texture-filter parameters. Texture-filter parameters are calculated by generating a first and a second pair of screen-space basis vectors being rotated relative to each other. First and second pairs of texture-space basis vectors are calculated that correspond to the first and second pairs of screen-space basis vectors transformed to texture space under a local approximation of a mapping between screen space and texture space. An angular displacement is determined between a selected pair of the first and second pairs of screen-space basis vectors and screen-space principal axes of a local approximation of the mapping that indicate the maximum and minimum scale factors of the mapping.Type: GrantFiled: October 19, 2020Date of Patent: January 4, 2022Assignee: Imagination Technologies LimitedInventor: Rostam King