Abstract: Foveated rendering for rendering an image uses a ray tracing technique to process graphics data for a region of interest of the image, and a rasterisation technique is used to process graphics data for other regions of the image. A rendered image can be formed using the processed graphics data for the region of interest of the image and the processed graphics data for the other regions of the image. The region of interest may correspond to a foveal region of the image. Ray tracing naturally provides high detail and photo-realistic rendering, which human vision is particularly sensitive to in the foveal region; whereas rasterisation techniques are suited for providing temporal smoothing and anti-aliasing in a simple manner, and is therefore suited for use in the regions of the image that a user will see in the periphery of their vision.

Abstract: Described herein are hardware monitors arranged to detect illegal firmware instructions in a firmware binary image using a hardware design and one or more formal assertions. The hardware monitors include monitor and detection logic configured to detect when an instantiation of the hardware design has started and/or stopped execution of the firmware and to detect when the instantiation of the hardware design has decoded an illegal firmware instruction. The hardware monitors also include assertion evaluation logic configured to determine whether the firmware binary image comprises an illegal firmware instruction by evaluating one or more assertions that assert that if a stop of firmware execution has been detected, that a decode of an illegal firmware instruction has (or has not) been detected.

Abstract: A memory management system for generating 3-dimensional computer images is provided. The memory management system includes a device for subdividing an image into a plurality of rectangular areas, a memory for storing object data pertaining to objects in the image which fall in each rectangular area, a device for storing the object data in the memory, a device for deriving image data and shading data for each rectangular area from the object data, a device for supplying object data for each rectangular area from the respective portion of the memory and, if the rectangular area contains objects also falling in at least one other rectangular area, also from the global list, to the deriving device, and a device for storing the image data and shading data derived by the deriving device for display. The memory includes at least one portion allocated to each rectangular area and at least one portion allocated as a global list.

Abstract: A controller for an acoustic echo canceller includes a noise estimator configured to estimate a level of noise that is comprised in a microphone signal relative to an echo component, estimated by the acoustic echo canceller, comprised in the microphone signal. The controller further includes a control module configured to control the acoustic echo canceller in dependence on that estimate.

Abstract: A communications interface for interfacing between a host system and a state machine includes an event slot, the event slot comprising a plurality of registers including: a write register for writing by the host system, and a read register for reading by the host system, wherein the event slot is addressed from the host system by a single address location permitting the host system to write data to the write register and/or read data from the read register; and wherein the write register and the read register are individually addressable by the state machine.

Abstract: Address generators for use in verifying an integrated circuit hardware design for an n-way set associative cache. The address generator is configured to generate, from a reverse hashing algorithm matching the hashing algorithm used by the n-way set associative cache, a list of cache set addresses that comprises one or more addresses of the main memory corresponding to each of one or more target sets of the n-way set associative cache. The address generator receives requests for addresses of main memory from a driver to be used to generate stimuli for testing an instantiation of the integrated circuit hardware design for the n-way set associative cache. In response to receiving a request the address generator provides an address from the list of cache set addresses.

Abstract: A memory subsystem for use with a single-instruction multiple-data (SIMD) processor comprising a plurality of processing units configured for processing one or more workgroups each comprising a plurality of SIMD tasks, the memory subsystem comprising: a shared memory partitioned into a plurality of memory portions for allocation to tasks that are to be processed by the processor; and a resource allocator configured to, in response to receiving a memory resource request for first memory resources in respect of a first-received task of a workgroup, allocate to the workgroup a block of memory portions sufficient in size for each task of the workgroup to receive memory resources in the block equivalent to the first memory resources.

Abstract: Rendering systems that can use combinations of rasterization rendering processes and ray tracing rendering processes are disclosed. In some implementations, these systems perform a rasterization pass to identify visible surfaces of pixels in an image. Some implementations may begin shading processes for visible surfaces, before the geometry is entirely processed, in which rays are emitted. Rays can be culled at various points during processing, based on determining whether the surface from which the ray was emitted is still visible. Rendering systems may implement rendering effects as disclosed.

Abstract: A synchronisation symbol detector that comprises two correlation modules and a comparison module. The first correlation module performs one or more correlations between the input signal and a down-converted version of the input signal and generates a first correlation metric from the one or more first correlations. The second correlation module performs one or more second correlations between the input signal and an up-converted version of the input signal and generates a second correlation metric from the one or more second correlations. The comparison module is configured to compare the first correlation metric and the second correlation metric and determine whether the input signal comprises a synchronisation symbol based on the comparison.

Abstract: Methods and systems for verifying, via formal verification, a hardware design for a data transformation pipeline comprising one or more data transformation elements that perform a data transformation on one or more inputs, wherein the formal verification is performed under conditions that simplify the data transformations calculations that the formal verification tool has to perform. In one embodiment the hardware design for the data transformation pipeline is verified by formally verifying that the output of an instantiation of the hardware design produces the same output as an instantiation of a hardware design for another data transformation pipeline for a predetermined set of transactions under a constraint that substantially equivalent data transformation elements between the data transformation pipelines produce the same output(s) in response to the same input(s).

Abstract: Methods for converting an n-bit number into an m-bit number for situations where n>m and also for situations where n<m, where n and m are integers. The methods use truncation or bit replication followed by the calculation of an adjustment value which is applied to the replicated number.

Abstract: In an aspect, a processor includes circuitry for iterative refinement approaches, e.g., Newton-Raphson, to evaluating functions, such as square root, reciprocal, and for division. The circuitry includes circuitry for producing an initial approximation; which can include a LookUp Table (LUT). LUT may produce an output that (with implementation-dependent processing) forms an initial approximation of a value, with a number of bits of precision. A limited-precision multiplier multiplies that initial approximation with another value; an output of the limited precision multiplier goes to a full precision multiplier circuit that performs remaining multiplications required for iteration(s) in the particular refinement process being implemented. For example, in division, the output being calculated is for a reciprocal of the divisor.

Abstract: Hardware logic arranged to normalise (or renormalise) an n-bit input number is described in which at least a proportion of a left shifting operation is performed in parallel with a leading zero count operation. In various embodiments the left shifting and the leading zero count are performed independently. In various other embodiments, a subset of the bits output by a leading zero counter are input to a left shifter and the output from the left shifter is input to a renormalisation block which completes the remainder of the left shifting operation independently of any further input from the leading zero counter.

Abstract: Data compression (and corresponding decompression) is used to compress blocks of data values involving processes including one or more of colour decorrelation, spatial decorrelation, entropy encoding and packing. The entropy encoding generates encoded data values which have variable sizes (in terms of the number of bits). The entropy encoding uses size indications for respective sets of data values to indicate the number of bits used for the encoded data values of the set. The size indications allow the encoded data values to be parsed quickly (e.g. in parallel).

Abstract: Hardware tessellation units include a sub-division logic block that comprises hardware logic arranged to perform a sub-division of a patch into two (or more) sub-patches. The hardware tessellation units also include a decision logic block that is configured to determine whether a patch is to be sub-divided or not and one or more hardware elements that control the order in which tessellation occurs. In various examples, this hardware element is a patch stack that operates a first-in-last-out scheme and in other examples, there are one or more selection logic blocks that are configured to receive patch data for more than one patch or sub-patch and output the patch data for a selected one of the received patches or sub-patches.

Abstract: A ray-tracing system configured to perform intersection testing, comprising: a tester module for testing rays for intersection with a volume, the tester module being configured to receive a packet of one or more rays to be tested for intersection with the volume, wherein the tester module comprises: a first set of one or more testers configured to perform intersection testing at a first level of precision to provide intersection testing results, wherein for a first type of the intersection testing result from the first set of one or more testers intersection testing does not need to be reperformed at a second level of precision greater than the first level of precision, and for a second type of the intersection testing result from the first set of one or more testers intersection testing is to be reperformed at the second level of precision; and a second set of one or more testers configured to perform intersection testing at the second level of precision; wherein the tester module is configured to: allocate

Abstract: Aspects relate to tracing rays in 3-D scenes that comprise objects that are defined by or with implicit geometry. In an example, a trapping element defines a portion of 3-D space in which implicit geometry exist. When a ray is found to intersect a trapping element, a trapping element procedure is executed. The trapping element procedure may comprise marching a ray through a 3-D volume and evaluating a function that defines the implicit geometry for each current 3-D position of the ray. An intersection detected with the implicit geometry may be found concurrently with intersections for the same ray with explicitly-defined geometry, and data describing these intersections may be stored with the ray and resolved.

Abstract: A data compression method comprises encoding groups of data items by generating, for each group, header data comprising h-bits and a plurality of body portions each comprising b-bits and each body portion corresponding to a data item in the group. The value of h may be fixed for all groups and the value of b is fixed within a group, wherein the header data for a group comprises an indication of b for the body portions of that group. In various examples, b=0 and so there are no body portions. In examples where b is not equal to zero, a body data field is generated for each group by interleaving bits from the body portions corresponding to data items in the group. The resultant encoded data block, comprising the header data and, where present, the body data field can be written to memory.

Abstract: A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in the hardware design; and property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the hardware design in completing the symbolic task. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design meets a desired performance goal and/or to exhaustively identify a performance metric (e.g. best case and/or worst case performance) with respect to completion of the task.

Abstract: A video packet stream is transmitted from a transmitting device to a receiving device over a network, by transmitting an audio packet stream to the receiving device, determining a measure of network bandwidth in dependence on one or more metrics associated with receiving the audio packet stream at the receiving device, and enabling a video packet stream in dependence on the determined measure.