Patents Assigned to Imagination Technologies
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Patent number: 10942986Abstract: Hardware implementations of, and methods for processing, a convolution layer of a DNN that comprise a plurality of convolution engines wherein the input data and weights are provided to the convolution engines in an order that allows input data and weights read from memory to be used in at least two filter-window calculations performed either by the same convolution engine in successive cycles or by different convolution engines in the same cycle. For example, in some hardware implementations of a convolution layer the convolution engines are configured to process the same weights but different input data each cycle, but the input data for each convolution engine remains the same for at least two cycles so that the convolution engines use the same input data in at least two consecutive cycles.Type: GrantFiled: November 2, 2018Date of Patent: March 9, 2021Assignee: Imagination Technologies LimitedInventors: Chris Martin, David Hough, Clifford Gibson, Daniel Barnard
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Patent number: 10943386Abstract: Systems and methods of geometry processing, for rasterization and ray tracing processes provide for pre-processing of source geometry, such as by tessellating or other procedural modification of source geometry, to produce final geometry on which a rendering will be based. An acceleration structure (or portion thereof) for use during ray tracing is defined based on the final geometry. Only coarse-grained elements of the acceleration structure may be produced or retained, and a fine-grained structure within a particular coarse-grained element may be Produced in response to a collection of rays being ready for traversal within the coarse grained element. Final geometry can be recreated in response to demand from a rasterization engine, and from ray intersection units that require such geometry for intersection testing with primitives. Geometry at different resolutions can be generated to respond to demands from different rendering components.Type: GrantFiled: May 21, 2018Date of Patent: March 9, 2021Assignee: Imagination Technologies LimitedInventors: John W. Howson, Luke T. Peterson
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Patent number: 10936509Abstract: A memory interface for interfacing between a memory bus addressable using a physical address space and a cache memory addressable using a virtual address space, the memory interface comprising: a memory management unit configured to maintain a mapping from the virtual address space to the physical address space; and a coherency manager comprising a reverse translation module configured to maintain a mapping from the physical address space to the virtual address space; wherein the memory interface is configured to: receive a memory read request from the cache memory, the memory read request being addressed in the virtual address space; translate the memory read request, at the memory management unit, to a translated memory read request addressed in the physical address space for transmission on the memory bus; receive a snoop request from the memory bus, the snoop request being addressed in the physical address space; and translate the snoop request, at the coherency manager, to a translated snoop request addrType: GrantFiled: March 15, 2018Date of Patent: March 2, 2021Assignee: Imagination Technologies LimitedInventors: Martin John Robinson, Mark Landers
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Patent number: 10937234Abstract: Viewport transformation modules for use in a three-dimensional rendering system wherein vertices are received from an application in a strip. The viewport transformation modules include a fetch module configured to read from a vertex buffer: untransformed coordinate data for a vertex in a strip; information identifying a viewport associated with the vertex; and information identifying a viewport associated with one or more other vertices in the strip. The one or more other vertices in the strip are selected based on a provoking vertex of a primitive to be formed by the vertices in the strip and a number of vertices in the primitive. The viewport transformation modules also include a processing module that performs a viewport transformation on the untransformed coordinate data based on each of the identified viewports to generate transformed coordinate data for each identified viewport; and a write module that writes the transformed coordinate data for each identified viewport to the vertex buffer.Type: GrantFiled: May 11, 2020Date of Patent: March 2, 2021Assignee: Imagination Technologies LimitedInventor: Jairaj Dave
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Patent number: 10937198Abstract: A decoder is configured to decode a plurality of texels from a received block of texture data encoded according to the Adaptive Scalable Texture Compression (ASTC) format, and includes a parameter decode unit configured to decode configuration data for the received block of texture data, a colour decode unit configured to decode colour endpoint data for the plurality of texels of the received block in dependence on the configuration data, a weight decode unit configured to decode interpolation weight data for each of the plurality of texels of the received block in dependence on the configuration data, and at least one interpolator unit configured to calculate a colour value for each of the plurality of texels of the received block using the interpolation weight data for that texel and a pair of colour endpoints from the colour endpoint data.Type: GrantFiled: April 28, 2018Date of Patent: March 2, 2021Assignee: Imagination Technologies LimitedInventors: Kenneth Rovers, Yoong Chert Foo
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Patent number: 10937228Abstract: Implementations of blender hardware perform both domain shading and blending and whilst some vertices may not require blending, all vertices require domain shading. The blender hardware includes a cache and/or a content addressable memory and these data structures are used to reduce duplicate domain shading operations.Type: GrantFiled: April 5, 2019Date of Patent: March 2, 2021Assignee: Imagination Technologies LimitedInventors: Peter Malcolm Lacey, Simon Fenney, Tobias Hector, Ian King
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Patent number: 10939398Abstract: A method at a first device for synchronising a first clock of the first device to a second clock of a second device, includes receiving a first message comprising an identifier from a third device; generating a first timestamp in dependence on the time at which the first message is received at the first device according to the first clock; receiving a second message from the second device comprising the identifier and a second timestamp, the second timestamp having been generated in dependence on the time at which the second device received the first message from the third device according to the second clock; and adjusting the first clock in dependence on a time difference between a time indicated by the first timestamp and a time indicated by the second timestamp.Type: GrantFiled: June 3, 2019Date of Patent: March 2, 2021Assignee: Imagination Technologies LimitedInventors: Arnold Mark Bilstad, Jose Juan Fernandez Dios, Paul Matthew Blay
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Patent number: 10939402Abstract: A high definition timing synchronization function is described. In an embodiment, a wireless station generates a time stamp at a higher resolution than can be broadcast within a standard time stamp field in a frame. The generated time stamp is divided into two parts: the first part being included within the time stamp field and the second part being included within a vendor specific field in the same frame. The frame is transmitted by the wireless station and received by other wireless stations in the wireless network. If the receiving wireless station has the capability, it decodes both the time stamp field and the vendor specific field and recreates the higher resolution time stamp. This higher resolution time stamp is then used to synchronize the receiving wireless station and the transmitting wireless station by resetting a clock or by storing time stamps and corresponding clock values.Type: GrantFiled: May 20, 2019Date of Patent: March 2, 2021Assignee: Imagination Technologies LimitedInventor: Ian Knowles
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Patent number: 10936775Abstract: A hardware monitor arranged to detect out-of-bounds violations in a hardware design for an electronic device. The hardware monitors include monitor and detection logic configured to monitor the current operating state of an instantiation of the hardware design and detect when the instantiation of the hardware design implements a fetch of an instruction from memory; and assertion evaluation logic configured to evaluate one or more assertions that assert a formal property that compares the memory address of the fetched instruction to an allowable memory address range associated with the current operating state of the instantiation of the hardware design to determine whether there has been an out-of-bounds violation. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design does not cause an instruction to be fetched from an out-of-bounds address.Type: GrantFiled: July 16, 2020Date of Patent: March 2, 2021Assignee: Imagination Technologies LimitedInventors: Ashish Darbari, Iain Singleton
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Patent number: 10929583Abstract: Methods and systems for verifying a derived clock using assertion-based verification. The method comprises counting the number of full or half cycles of a fast clock that occur between the rising edge and the falling edge of a slow clock (i.e. during the ON phase of the slow clock); counting the number of full or half cycles of the fast clock that occur between the falling edge and the rising edge of the slow clock (i.e. during the OFF phase of the slow clock); and verifying the counts using assertion-based verification.Type: GrantFiled: June 14, 2019Date of Patent: February 23, 2021Assignee: Imagination Technologies LimitedInventor: Ashish Darbari
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Patent number: 10930052Abstract: Systems and methods for producing an acceleration structure provide for subdividing a 3-D scene into a plurality of volumetric portions, which have different sizes, each being addressable using a multipart address indicating a location and a relative size of each volumetric portion. A stream of primitives is processed by characterizing each according to one or more criteria, selecting a relative size of volumetric portions for use in bounding the primitive, and finding a set of volumetric portions of that relative size which bound the primitive. A primitive ID is stored in each location of a cache associated with each volumetric portion of the set of volumetric portions. A cache location is selected for eviction, responsive to each cache eviction decision made during the processing. An element of an acceleration structure according to the contents of the evicted cache location is generated, responsive to the evicted cache location.Type: GrantFiled: January 10, 2019Date of Patent: February 23, 2021Assignee: Imagination Technologies LimitedInventors: James A. McCombe, Aaron Dwyer, Luke T. Peterson, Neils Nesse
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Patent number: 10929138Abstract: An on-chip cache is described which receives memory requests and in the event of a cache miss, the cache generates memory requests to a lower level in the memory hierarchy (e.g. to a lower level cache or an external memory). Data returned to the on-chip cache in response to the generated memory requests may be received out-of-order. An instruction scheduler in the on-chip cache stores pending received memory requests and effects the re-ordering by selecting a sequence of pending memory requests for execution such that pending requests relating to an identical cache line are executed in age order and pending requests relating to different cache lines are executed in an order dependent upon when data relating to the different cache lines is returned. The memory requests which are received may be received from another, lower level on-chip cache or from registers.Type: GrantFiled: June 13, 2017Date of Patent: February 23, 2021Assignee: Imagination Technologies LimitedInventors: Mark Landers, Martin John Robinson
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Patent number: 10924695Abstract: Image processing systems and methods are provided for processing a stream of data values (e.g. pixel values). The image processing system comprises a processing module configured to: receive a plurality of pixel values, each of the received pixel values having a first number of bits; and implement processing of a particular pixel value by operating on a particular subset of the received pixel values, by: classifying each of the pixel values within the particular subset into a group of a set of one or more groups; determining an average value in respect of the pixel values within the particular subset which are classified into one of the one or more groups, wherein the determined average value has a second number of bits, wherein said second number is greater than said first number; replacing the particular pixel value based on the determined average value; and outputting the processed particular pixel value.Type: GrantFiled: October 30, 2018Date of Patent: February 16, 2021Assignee: Imagination Technologies LimitedInventor: Timothy Lee
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Patent number: 10922873Abstract: During tracing of a primary ray in a 3-D space (e.g., a 3-D scene in graphics rendering), a ray is found to intersect a primitive (e.g., a triangle) located in the 3-D space. Secondary ray(s) may be generated for a variety of purposes. For example, occlusion rays may be generated to test occlusion of a point of intersection between the primary ray and primitive is illuminated by any of the light(s). An origin for each secondary ray can be modified from the intersection point based on characteristics of the primitive intersected. For example, an offset from the intersection point can be calculated using barycentric coordinates of the intersection point and interpolation of one or more parameters associated with vertices defining the primitive. These parameters may include a size of the primitive and differences between a geometric normal for the primitive and a respective additional vector supplied with each vertex.Type: GrantFiled: September 17, 2019Date of Patent: February 16, 2021Assignee: Imagination Technologies LimitedInventor: Aaron Dwyer
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Patent number: 10908945Abstract: A converter module is described which handles memory requests issued by a cache (e.g. an on-chip cache), where these memory requests include memory addresses defined within a virtual memory space. The converter module receives these requests, issues each request with a transaction identifier and uses that identifier to track the status of the memory request. The converter module sends requests for address translation to a memory management unit and where there the translation is not available in the memory management unit receives further memory requests from the memory management unit. The memory requests are issued to a memory via a bus and the transaction identifier for a request is freed once the response has been received from the memory. When issuing memory requests onto the bus, memory requests received from the memory management unit may be prioritized over those received from the cache.Type: GrantFiled: January 18, 2019Date of Patent: February 2, 2021Assignee: Imagination Technologies LimitedInventors: Mark Landers, Martin John Robinson
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Patent number: 10909742Abstract: A method of controlling the order in which primitives generated during tessellation are output by the tessellation unit involves sub-dividing a patch, selecting one of the two sub-patches which are formed by the sub-division and tessellating that sub-patch until no further sub-division is possible before tessellating the other (non-selected) sub-patch. The method is recursively applied at each level of sub-division. Patches are output as primitives at the point in the method where they do not require any further sub-division. The selection of a sub-patch is made based on the values of one or more flags and any suitable tessellation method may be used to determine whether to sub-divide a patch. Methods of controlling the order in which vertices are output by the tessellation unit are also described and these may be used in combination with, or independently of, the method of controlling the primitive order.Type: GrantFiled: April 5, 2019Date of Patent: February 2, 2021Assignee: Imagination Technologies LimitedInventor: Peter Malcolm Lacey
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Patent number: 10909745Abstract: A graphics processor architecture provides for scan conversion and ray tracing approaches to visible surface determination as concurrent and separate processes. Surfaces can be identified for shading by scan conversion and ray tracing. Data produced by each can be normalized, so that instances of shaders, being executed on a unified shading computation resource, can shade surfaces originating from both ray tracing and rasterization. Such resource also may execute geometry shaders. The shaders can emit rays to be tested for intersection by the ray tracing process. Such shaders can complete, without waiting for those emitted rays to complete. Where scan conversion operates on tiles of 2-D screen pixels, the ray tracing can be tile aware, and controlled to prioritize testing of rays based on scan conversion status. Ray population can be controlled by feedback to any of scan conversion, and shading.Type: GrantFiled: January 15, 2019Date of Patent: February 2, 2021Assignee: Imagination Technologies LimitedInventors: John W. Howson, Luke Tilman Peterson, Steven J. Clohset
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Patent number: 10908877Abstract: Median values for a stream of received data values in a data processing system (e.g. an image processing system) are determined. A first median value of the received data values within a first subset of data values of the received stream is determined, and intermediate data used for determining the first median value is stored. The stored intermediate data is used to determine a median value of the received data values within a second subset of data values of the received stream, wherein the second subset at least partially overlaps with the first subset. The determined median values are outputted for use in the data processing system, e.g. for further processing.Type: GrantFiled: October 2, 2019Date of Patent: February 2, 2021Assignee: Imagination Technologies LimitedInventor: Timothy Lee
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Patent number: 10909289Abstract: A hardware monitor arranged to detect livelock in a hardware design for an integrated circuit. The hardware monitor includes monitor and detection logic configured to detect when a particular state has occurred in an instantiation of the hardware design; and assertion evaluation logic configured to periodically evaluate one or more assertions that assert a formal property related to reoccurrence of the particular state in the instantiation of the hardware design to detect whether the instantiation of the hardware design is in a livelock comprising the predetermined state. The hardware monitor may be used by a formal verification tool to exhaustively verify that the instantiation of the hardware design cannot enter a livelock comprising the predetermined state.Type: GrantFiled: May 22, 2019Date of Patent: February 2, 2021Assignee: Imagination Technologies LimitedInventors: Ashish Darbari, Iain Singleton
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Patent number: 10901922Abstract: Methods and arbiter systems for arbitrating between a plurality of ordered requestors and a shared resource based on priorities allocated to the requestors include determining whether there is at least one requestor that has requested access in the current cycle and has priority in the current cycle. In response to determining that there is at least one requestor that has requested access in the current cycle and has priority in the current cycle, a lowest ordered requestor is selected that has requested access in the current cycle and has priority in the current cycle; and in response to determining that there are no requestors that have requested access in the current cycle and have priority in the current cycle, a highest ordered requestor is selected that has requested access in the current cycle.Type: GrantFiled: March 25, 2019Date of Patent: January 26, 2021Assignee: Imagination Technologies LimitedInventor: Jonas Olof Gunnar Källén