Patents Assigned to Imagination Technologies
  • Rendering of soft shadows
    Patent number: 10628992
    Abstract: Systems can identify visible surfaces for pixels in an image (portion) to be rendered. A sampling pattern of ray directions is applied to the pixels, so that the sampling pattern of ray directions repeats, and with respect to any pixel, the same ray direction can be found in the same relative position, with respect to that pixel, as for other pixels. Rays are emitted from visible surfaces in the respective ray direction supplied from the sampling pattern. Ray intersections can cause shaders to execute and contribute results to a sample buffer. With respect to shading of a given pixel, ray results from a selected subset of the pixels are used; the subset is selected by identifying a set of pixels, collectively from which rays were traced for the ray directions in the pattern, and requiring that surfaces from which rays were traced for those pixels satisfy a similarity criteria.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: April 21, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Gareth Morgan, Luke T. Peterson
  • Modulo hardware generator
    Patent number: 10628125
    Abstract: A method of generating a hardware design to calculate a modulo value for any input value in a target input range with respect to a constant value d using one or more range reduction stages. The hardware design is generated through an iterative process that selects the optimum component for mapping successively increasing input ranges to the target output range until a component is selected that maps the target input range to the target output range. Each iteration includes generating hardware design components for mapping the input range to the target output range using each of a plurality of modulo preserving range reduction methods, synthesizing the generated hardware design components, and selecting one of the generated hardware design components based on the results of the synthesis.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: April 21, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Samuel Lee
  • Sorting memory address requests for parallel memory access
    Patent number: 10628341
    Abstract: Apparatus identifies a set of M output memory addresses from a larger set of N input memory addresses containing at least one non-unique memory address. A comparator block performs comparisons of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresses from the set of input addresses, where each address in the subset identified by the binary classification dataset is unique within that subset. Combination logic units receive a predetermined selection of bits of the binary classification dataset and sort its received predetermined selection of bits into an intermediary binary string in which the bits are ordered into a first group identifying addresses belonging to the identified subset, and a second group identifying addresses not belonging to the identified subset.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: April 21, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Luca Iuliano, Simon Nield, Thomas Rose
  • Untransformed display lists in a tile based rendering system
    Patent number: 10621775
    Abstract: 3-D rendering systems include a rasterization section that can fetch untransformed geometry, transform geometry and cache data for transformed geometry in a memory. As an example, the rasterization section can transform the geometry into screen space. The geometry can include one or more of static geometry and dynamic geometry. The rasterization section can query the cache for presence of data pertaining to a specific element or elements of geometry, and use that data from the cache, if present, and otherwise perform the transformation again, for actions such as hidden surface removal. The rasterization section can receive, from a geometry processing section, tiled geometry lists and perform the hidden surface removal for pixels within respective tiles to which those lists pertain.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: April 14, 2020
    Assignee: Imagination Technologies Limited
    Inventor: John W. Howson
  • Method and system for multisample antialiasing
    Patent number: 10614622
    Abstract: A method and system for generating two or three dimensional computer graphics images using multisample antialiasing (MSAA) is provided, which enables memory bandwidth to be conserved. For each of one or more pixels it is determined whether all of a plurality of sample areas of that pixel are located within a particular primitive. For those pixels where it is determined that all the sample areas of that pixel are located within that primitive, a value is stored in a multisample memory for a smaller number of the sample areas of that pixel than the total number of the sample areas of that pixel and data is stored indicating that all the sample areas of that pixel are located within that primitive.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: April 7, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Yoong Chert Foo, Salil Sahasrabudhe, Andrew Davy
  • Camera calibration
    Patent number: 10609281
    Abstract: A method of calibrating a camera performs a first calibration for frames of a sequence captured by the camera to calculate for those frames first calibration data for a set of one or more camera parameters; performs, for selected frames of the sequence, a second calibration to calculate second calibration data for the selected frames in dependence on the first calibration data for those frames; and uses the second calibration data in the first calibration performed for subsequent frames of the sequence.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: March 31, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Timothy Smith
  • Error bounded multiplication by invariant rationals
    Patent number: 10606558
    Abstract: A hardware logic representation of a circuit to implement an operation to perform multiplication by an invariant rational is generated by truncating an infinite single summation array (which is represented in a finite way). The truncation is performed by identifying a repeating section and then discarding all but a finite number of the repeating sections whilst still satisfying a defined error bound. To further reduce the size of the summation array, the binary representation of the invariant rational is converted into canonical signed digit notation prior to creating the finite representation of the infinite array.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: March 31, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Theo Alan Drane
  • Method and apparatus for rendering a computer generated image
    Patent number: 10600241
    Abstract: A method and apparatus for rendering a computer-generated image using a stencil buffer is described. The method divides an arbitrary closed polygonal contour into first and higher level primitives, where first level primitives correspond to contiguous vertices in the arbitrary closed polygonal contour and higher level primitives correspond to the end vertices of consecutive primitives of the immediately preceding primitive level. The method reduces the level of overdraw when rendering the arbitrary polygonal contour using a stencil buffer compared to other image space methods. A method of producing the primitives in an interleaved order, with second and higher level primitives being produced before the final first level primitives of the contour, is described which improves cache hit rate by reusing more vertices between primitives as they are produced.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: March 24, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney
  • Augmented reality occlusion
    Patent number: 10600247
    Abstract: A method for generating an augmented reality image from first and second images, wherein at least a portion of at least one of the first and the second image is captured from a real scene, the method comprising: identifying a confidence region in which a confident determination as to which of the first and second image to render in that region of the augmented reality image can be made; identifying an uncertainty region in which it is uncertain as to which of the first and second image to render in that region of the augmented reality image; determining at least one blending factor value in the uncertainty region based upon a similarity between a first colour value in the uncertainty region and a second colour value in the confidence region; and generating an augmented reality image by combining, in the uncertainty region, the first and second images using the at least one blending factor value.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: March 24, 2020
    Assignee: Imagination Technologies Limited
    Inventor: David Walton
  • Communications interface circuit architecture
    Patent number: 10599595
    Abstract: A communications interface for interfacing between a host system and a state machine, the communications interface comprising: an event slot, the event slot comprising a plurality of registers including: a write register for writing by the host system, and a read register for reading by the host system, wherein the event slot is addressed from the host system by a single address location permitting the host system to write data to the write register and/or read data from the read register; and wherein the write register and the read register are individually addressable by the state machine.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: March 24, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Bert Hindle, Ben Fletcher
  • Identifying network conditions
    Patent number: 10587518
    Abstract: A method of identifying a network condition between a pair of network devices, the method comprising: determining a first time period between receiving a first-received packet for an initial media frame and receiving a first-received packet for a subsequent media frame, wherein the packets are received at one of the devices via a network and each received packet comprises a timestamp; determining a second time period between the timestamp of the packet for the initial media frame and the timestamp of the packet for the subsequent media frame; and identifying a network condition in dependence on a difference between the first and second time periods.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: March 10, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Kiran Kumar Ravuri
  • Bandwidth Management
    Patent number: 10587523
    Abstract: A video packet stream is transmitted from a transmitting device to a receiving device over a network, by transmitting an audio packet stream to the receiving device, determining a measure of network bandwidth in dependence on one or more metrics associated with receiving the audio packet stream at the receiving device, and enabling a video packet stream in dependence on the determined measure.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: March 10, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Senthil Kumar Mani, Bala Manikya Prasad Puram
  • Multi-phased and multi-threaded program execution based on SIMD ratio
    Patent number: 10585700
    Abstract: A microprocessor is configured to execute programs divided into discrete phases. A scheduler is provided for scheduling instructions. A plurality of resources are for executing instructions issued by the scheduler, wherein the scheduler is configured to schedule each phase of the program only after receiving an indication that execution of the preceding phase of the program has been completed. By splitting programs into multiple phases and providing a scheduler that is able to determine whether execution of a phase has been completed, each phase can be separately scheduled and the results of preceding phases can be used to inform the scheduling of subsequent phases. In one example, different numbers of threads and/or different numbers of data instances per thread may be processed for different phases of the same program.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: March 10, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Yoong Chert Foo
  • Image filtering based on image gradients
    Patent number: 10580120
    Abstract: Image processing methods and systems apply filtering operations to images, wherein the filtering operations use filter costs which are based on image gradients in the images. In this way, image data is filtered for image regions in dependence upon the image gradients for the image regions. This may be useful for different scenarios such as when combining images to form a High Dynamic Range (HDR) image. The filtering operations may be used as part of a connectivity unit which determines connected image regions, and/or the filtering operations may be used as part of a blending unit which blends two or more images together to form a blended image.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: March 3, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Ruan Lakemond
  • Encoding and decoding variable length instructions
    Patent number: 10579381
    Abstract: Methods of encoding and decoding are described which use a variable number of instruction words to encode instructions from an instruction set, such that different instructions within the instruction set may be encoded using different numbers of instruction words. To encode an instruction, the bits within the instruction are re-ordered and formed into instruction words based upon their variance as determined using empirical or simulation data. The bits in the instruction words are compared to corresponding predicted values and some or all of the instruction words that match the predicted values are omitted from the encoded instruction.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: March 3, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Simon Thomas Nield, James McCarthy
  • Hardware monitor to verify memory units
    Patent number: 10580511
    Abstract: Hardware monitors which can be used by a formal verification tool to exhaustively verify a hardware design for a memory unit. The hardware monitors include detection logic to monitor one or more control signals and/or data signals of an instantiation of the memory unit to detect symbolic writes and symbolic reads. In some examples a symbolic write is a write of symbolic data to a symbolic address; and in other examples a symbolic write is a write of any data to a symbolic address. A symbolic read is a read of the symbolic address. The hardware monitors also include assertion verification logic that verifies an assertion that read data corresponding to a symbolic reads matches write data associated with one or more symbolic writes preceding the read.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: March 3, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Ashish Darbari, Iain Singleton
  • Performing object detection in an image
    Patent number: 10572756
    Abstract: A single-instruction, multiple data processor performs object detection in an image by testing for a plurality of object features in a plurality of image regions, the processor comprising: a set of computation units operable to execute a plurality of classifier sequences in parallel, each classifier sequence comprising a plurality of classifier routines, and each classifier routine comprising identical instructions to the other classifier routines in each of the plurality of classifier sequences; wherein each computation unit is configured to independently maintain data identifying an image region and a feature under test on that computation unit, and each classifier routine is arranged to access the data, test the identified feature against the identified image region and update the data such that the computation units are operable to concurrently test different features against different image regions.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: February 25, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Szabolcs Csèfalvay
  • Graphics processing units and methods for controlling rendering complexity using cost indications for sets of tiles of a rendering space
    Patent number: 10565772
    Abstract: A graphics processing unit (GPU) processes graphics data using a rendering space which is sub-divided into a plurality of tiles. The GPU comprises cost indication logic configured to obtain a cost indication for each of a plurality of sets of one or more tiles of the rendering space. The cost indication for a set of tile(s) is suggestive of a cost of processing the set of one or more tiles. The GPU controls a rendering complexity with which primitives are rendered in tiles based on the cost indication for those tiles. This allows tiles to be rendered in a manner that is suitable based on the complexity of the graphics data within the tiles. In turn, this allows the rendering to satisfy constraints such as timing constraints even when the complexity of different tiles may vary significantly within an image.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: February 18, 2020
    Assignee: Imagination Technologies Limited
    Inventors: John W. Howson, Richard Broadhurst, Steven Fishwick
  • Processing primitives which have unresolved fragments in a graphics processing system
    Patent number: 10559120
    Abstract: A graphics processing system performs hidden surface removal and texturing/shading on fragments of primitives. The system includes a primary depth buffer (PDB) for storing depth values of resolved fragments, and a secondary depth buffer (SDB) for storing depth values of unresolved fragments. Incoming fragments are depth tested against depth values from either the PDB or the SDB. When a fragment passes a depth test, its depth value is stored in the PDB if it is a resolved fragment (e.g. if it is opaque or translucent), and its depth value is stored in the SDB if it is an unresolved fragment (e.g. if it is a punch through fragment). This provides more opportunities for subsequent opaque objects to overwrite punch through fragments which passed a depth test, thereby reducing unnecessary processing and time which may be spent on fragments which ultimately will not contribute to the final rendered image.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: February 11, 2020
    Assignee: Imagination Technologies Limited
    Inventor: John Howson
  • Floating point to fixed point conversion
    Patent number: 10558428
    Abstract: A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2ew-1?1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: February 11, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Kenneth Rovers