Abstract: Devices and methods for junction formation in manufacturing a semiconductor device are disclosed. The devices have shallow junction depths far removed from end-of range defects. The method comprises forming an amorphous region in a crystalline semiconductor such as silicon down to a first depth, followed by implantation of a substitutional element such as carbon to a smaller depth than the first depth. The region is then doped with suitable dopants, e.g. phosphorus or boron, and the amorphous layer recrystallized by a thermal process.

Abstract: A multi-section laser diode control system comprising a multi-section laser diode (10), microprocessor controller (24), digital-to-analogue converter (28), driver circuit (30) and wavelength locker (14) is modified by inclusion of a locking circuit (40) which generates an analogue correction signal . . . 1 V ph responsive to measurements of the laser output made by the wavelength locker. The analogue correction signal is added to the preset phase voltage V ph asserted by the microprocessor controller to provide fast feedback that bypasses the microprocessor controller. This novel feedback is made possible by avoiding the use of the standard prior art control algorithm which requires a division calculation to be performed. Instead, novel control algorithms based purely on additions, subtractions and multiplications are used. The laser can thus be locked to its target output frequency without having to place slow analogue-to-digital and digital-to-analogue converters in the feedback control path.

Abstract: A method for forming deep via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), forming spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to narrow the opening, removing through said narrowed opening the remaining part of the sacrificial material (e.g. by isotropic etching) and finally sealing the opening of the airgap by depositing a conformal layer (TEOS) above the spacers. The method of forming a deep via airgap is used to create wafer to wafer vertical stacking. After completion of conventional FEOL and BEOL processing the backside of the wafer will be thinned such that the deep via airgap is opened and conductive material can be deposited within said (airgap) via opening and a through wafer or deep via filled with conductive material is created.

Abstract: A method for doping a multi-gate device is disclosed. In one aspect, the method comprises patterning a fin in a substrate, depositing a gate stack, and doping the fin. The process of doping the fin is done by depositing a blocking mask material at least on the top surface of the fin after the patterning of the gate stack. After the deposition of the blocking mask material dopant ions are implanted whereby the blocking mask material partially or completely blocks the top surface of the fin from these dopant ions.

Abstract: A method for doping a fin-based semiconductor device is disclosed. In one aspect, the method comprises patterning at least one fin, each fin comprising a top surface and a left sidewall surface and a right sidewall surface. The method further comprises providing a first target surface being the right sidewall of a first block of material. The method further comprises scanning a first primary ion beam impinging on the first target surface with an incident angle ? different from zero degrees and thereby inducing a first secondary ion beam, and doping at least the left sidewall surface and possibly the top surface of the fin opposite to the first target surface with the first secondary ion beam.

Abstract: A method for patterning high aspect ratio vias is provided. More specifically a dry etching method is provided for patterning deep vias or vias with high aspects ratios thereby eliminating the hard mask undercut. A method is provided to create (pattern) deep vias in a substrate for use in three dimensional stacked semiconductor devices and/or structures. More specifically, a method is provided for patterning deep vias with an aspect ratio up to 10 into a Si substrate with smooth via sidewalls and sufficient slope to enable metallization.

Abstract: An electrical device comprises analog conversion circuitry having an input and an output. The electrical device is essentially provided for converting a first input signal within a first frequency range applied to the input to a first output signal within a second frequency range different from the first frequency range at the output. The electrical device further comprises a signal adding means for adding at least a portion of the first output signal as second input signal to the first input signal. The analog conversion circuitry is also capable of converting the second input signal, which is within the second frequency range, back to the first frequency range. Additionally, a characteristic deriving means is provided for deriving at least one characteristic of the electrical device from the frequency converted second input signal, which appears at the output of the analog conversion circuitry.

Abstract: A technique is described for the preparation of polymers according to a new process, in which the starting compound of formula (I) is polymerized in the presence of a base, in an organic solvent. The precursor polymer such obtained comprises structural units of the formula (II). In a next step, the precursor polymer (II) is subjected to a conversion reaction by thermal treatment. The arylene or heteroarylene polymer comprises structural units of the formula III. In this new process the dithiocarbamate group acts as a leaving group and permits the formation of a precursor polymer of structural formula (II), which has an average molecular weight from 5.000 to 500.000 Dalton and is soluble in common organic solvents. The precursor polymer with structural units of formula (II) is thermally converted to the conjugated polymer with structural formula (III).

Abstract: A packaged microelectronic device (20) is provided comprising at least one electrode (10) comprising a chip (18) embedded in a package. The chip (18) comprises a back electrode (17) located at a first side of the chip (18), and electronic circuitry (14) located at a second side of the chip (18), the second side being opposite to the first side, and wherein the back electrode (17) is part of the package. A method for forming such packaged microelectronic devices (20) is also described.

Abstract: Non-volatile memory devices are disclosed. In a first example non-volatile memory device, programming and erasing of the memory device is performed through the same insulating barrier without the use of a complex symmetrical structure. In the example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to a charge storage region. Further in the example device, erasing is accomplished by tunneling positive carriers from the charge supply region to the charge storage region. In a second example non-volatile memory device, a charge storage region with spatially distributed charge storage region is included. Such a charge storage region may be implemented in the first example memory device or may be implemented in other memory devices. In the second example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to the charge storage region.

Abstract: A method of manufacturing a semiconductor device comprising a dual gate field effect transistor is disclosed, in which method a semiconductor body with a surface and of silicon is provided with a source region and a drain region of a first conductivity type and with a channel region of a second conductivity type, opposite to the first conductivity type, between the source region and the drain region and with a first gate region separated from the channel region by a first gate dielectric and situated on one side of the channel region and with a second gate region separated from the channel region by a second gate dielectric and situated on an opposite side of the channel region, and wherein both gate regions are formed within a trench formed in the semiconductor body.

Abstract: The present invention is related to a device comprising a substrate comprising a silicon substrate having a porous top layer, a second layer on said top layer, said second layer made of a material comprising Ge, and a further layer of a Group III-nitride material on the second layer. The present invention further is related to methods of production and to intermediate or template devices highly suitable for the epitaxial growth of a high quality Group III-nitride layer.

Abstract: A method is presented for determining an actual pulse position in a signal. This signal comprises a plurality of successive frames, wherein each frame has length L and contains one pulse with width W, a number of discrete possible pulse positions being considered within in each frame which is at least L/W. The method comprises the steps of a) sampling the signal at a sampling rate below L/W with a varying sampling phase such that the whole frame length L is covered, b) obtaining a set of samples with at least one at each of the possible pulse positions, c) correlating this set of samples with a set of one or more predetermined values and d) determining the actual pulse position from said correlation. The method provides a low-complex signal acquisition solution in a receiver and is particularly useful for low-complexity and low-power IR-UWB transceivers.

Abstract: A semiconductor device, fabricated by a method, having a semiconductor structure with a silicon region which forms at least one connection region in and/or on a surface of a substrate is disclosed. In one embodiment, the method includes i) forming, at least at the silicon region, a metal cluster layer from a first metal, such that, in the metal cluster layer, metal clusters alternate with sites where there are no metal clusters, the first metal being a non-siliciding metal at predetermined conditions, ii) depositing a metal layer of a second metal on top of the metal cluster layer, the second metal being a siliciding metal and iii) carrying out at least one heat treatment at the predetermined conditions on the second metal layer so as to form metal silicide through reaction of the second metal with the silicon region, wherein atoms of the first metal are displaced in a direction substantially perpendicular to the surface of the substrate.

Abstract: Electronic devices are disclosed that may be used for infrared radiation detection. An example electronic device includes a substrate, a transistor included in the substrate and a silicon-germanium (Si—Ge) structural layer coupled with the transistor. The structural layer has a stress in a predetermined range, where the predetermined range for the stress is selected prior to deposition of the structural layer. Also, the structural layer is deposited on the substrate subsequent to formation of the transistor such that deposition of the structural layer does not substantially adversely affect the operation of the transistor.

Abstract: Methods for the production of airgaps in semiconductor devices and devices produced using such methods are disclosed. An example semiconductor device includes a damascene stack formed using such methods. The damascene stack includes a patterned dielectric layer including an interconnect structure, where the dielectric layer is formed of a dielectric material including Si, C and O. The damascene stack also includes a converted portion of the dielectric layer, where the converted portion is adjacent to the at least one interconnect structure and has a lower carbon content than the dielectric material. The damascene stack also includes an airgap formed adjacent to the interconnect structure, the airgap being formed by removing at least part of the converted portion using an etch compound.

Abstract: A two-terminal organic light-emitting device structure is presented with low absorption losses and high current densities. Light generation and emission occur at a predetermined distance from any metallic contact, thereby reducing optical absorption losses. High current densities and thus high emitted light intensity are achieved by combining two types of conduction in one device: by combining space charge limited conduction and field-effect conduction or by combining ohmic conduction and field-effect conduction, thereby optimizing the current densities. This results in a very high local concentration of excitons and therefore a high light intensity, which can be important for applications such as organic lasers, and more in particular electrically pumped organic lasers.

Abstract: A method is disclosed for producing Group III-N field-effect devices, such as HEMT, MOSHFET, MISHFET or MESFET devices, comprising two active layers, e.g. a GaN/AlGaN layer. The method produces an enhancement mode device of this type, i.e. a normally-off device, by providing a passivation layer on the AlGaN layer, etching a hole in the passivation layer and not in the layers underlying the passivation layer, and depositing the gate contact in the hole, while the source and drain are deposited directly on the passivation layer. The characteristics of the active layers and/or of the gate are chosen such that no two-dimensional electron gas layer is present underneath the gate, when a zero voltage is applied to the gate. A device with this behavior is also disclosed.

Abstract: One inventive aspect relates to a method of determining an estimate of system-level yield loss for an electronic system comprising individual components subject to manufacturing process variability leading to manufacturing defects. The method comprises obtaining a description of the composition of the electronic system in terms of which individual components are used. The method further comprises obtaining statistical properties of the performance of individual components of the electronic system with respect to first and second performance variables, e.g. energy consumption and delay, the statistical properties including correlation information of the first and second performance variables. The method further comprises obtaining information about execution of an application on the system, e.g. a number of accesses of a component by an application.

Abstract: A method is disclosed for relaxing strain in a multi-gate device, the method comprising providing a substrate with a strained material, patterning a plurality of fins in the strained material, defining a first region comprising at least one fin, defining a second region comprising at least one fin, providing a diffusion barrier layer on the first region, performing a hydrogen anneal such that the strain in the second region is relaxed.