Abstract: A method is described for providing a predetermined optical path in an optical module, the predetermined optical path being defined by predetermined optical characteristics for the optical module. a modifiable optical element is provided at a predetermined position in the optical module, thus generating an initial optical path of the optical module. The modifiable optical element comprising at least one optical interface in the initial optical path. An optical signal is detected from a radiation beam on the initial optical path of the optical module. The optical interface of the modifiable optical element is then physically modified to generate at least one modified optical interface of the modifiable optical element. The physical modification takes into account the detected optical signal so as to obtain substantially the predetermined optical characteristics for the optical module.

Abstract: Micro electromechanical devices and methods for designing such devices are disclosed. An example micro electromechanical device includes at least two anchors. The example device also includes a floating element. The floating element extends between the at least two anchors and includes a predetermined reference portion. In at least one predetermined state during operation of the device, the reference portion is located within a predetermined reference plane. The floating element includes at least two flexible sections, where the at least two flexible sections each extends between the reference portion and a respective one of the anchors. In the example device, at least two of the at least two flexible sections include respective stress relieving elements. The stress relieving elements enable deflection of the floating element as a result of a stress gradient.

Abstract: A method for producing narrow trenches in semiconductor devices. The narrow trenches are formed by chemically changing the properties of a first dielectric layer locally, such that the side walls of a patterned hole in the first dielectric layer is converted locally and becomes etchable by a first etching substance. Subsequently a second dielectric material is deposited in the patterned structure and the damaged part of the first dielectric material is removed such that small trenches are obtained.

Abstract: A method is described for setting up lithographic processing of a substrate. The lithographic processing uses a bottom anti-reflective coating for minimizing the substrate reflectivity. Such bottom anti-reflective coating typically is characterized by a set of selectable BARC parameters, such as the thickness, real refractive index, and/or absorption coefficient. The method includes selecting a set of values for the BARC parameters, determining the substrate reflectivity in the resist layer using the selected BARC parameter values, thereby taking into account the angles of incidence of the incident light rays, and evaluating whether or not the selected BARC parameter values result in a sufficiently low substrate reflectivity. Preferably, together with taking into account the angles of incidence of the incident light rays, the amplitude and/or the polarization state for light rays having a different angle of incidence are also taken into account.

Abstract: In the present invention, a BARC stack comprising at least a first BARC layer and at least a second BARC layer is optimized for reducing substrate reflectivity in lithographic processing applications. The first BARC layer is positioned adjacent the resist layer, while the second BARC layer is positioned adjacent the first BARC layer. The optical parameters of the first BARC layer are determined to be slightly different from the optical parameters of the resist, thus resulting in a small optical step at the interface resist/first BARC. Furthermore, the second BARC may be selected to have optical parameters such that the optical step at the interface first BARC/second BARC is slightly larger but still relatively small compared to the optical step between resist and substrate. The thicknesses for the BARC layers can be determined from substrate reflectivity calculations. The latter allows obtaining a low substrate reflectivity for various pitches in a pattern to be printed.

Abstract: A method for designing an ESD protected analog circuit is described. The method includes creating an analog circuit design comprising a plurality of interconnected functional components and circuit-level ESD protection components with predetermined electric properties for achieving a predetermined analog performance during normal operation of the circuit as well as a predetermined ESD robustness during an ESD event on the circuit. At least one ESD event is simulated on the analog circuit design to identify at least one weak spot in the circuit. Component-level ESD protection components are added into the analog circuit design around each identified weak spot to reduce failure of the weak spot during an ESD event.

Abstract: A method is described for setting up the lithographic processing of a substrate. The lithographic processing typically is characterized by a set of selectable process parameters, such as the thickness, real refractive index, and absorption coefficient of a bottom anti-reflective layer. The method includes selecting a set of values for the selectable process parameters, determining the substrate reflectivity in the resist layer for these parameters, and evaluating if the determined substrate reflectivity is smaller than a maximum allowable substrate reflectivity in the resist layer. The maximum allowable substrate reflectivity is determined according to a floating criterion, i.e., the maximum allowable substrate reflectivity depends on a Normalized Image Log Slope related parameter.

Abstract: One embodiment of the invention relates to a method for fabricating a semiconductor device having a semiconductor structure with a silicon region which forms at least one connection region in and/or on a surface of a substrate. The method comprises forming a metal cluster layer from a first, non-siliciding metal, followed by the deposition of a metal layer consisting of a second, siliciding metal. A subsequent heat treatment is responsible for forming a metal silicide from the second metal, the atoms of the first metal being displaced in a direction substantially perpendicular to the surface of the substrate. According to one embodiment of the invention, the atoms of the first metal are displaced by the Kirkendall effect to beneath the metal silicide. If an MOST, for example, is being fabricated, this has advantages both at the location of the source and drain region and at the location of the gate electrode.

Abstract: The present invention is related to the realization of a simplified bottom electrode stack for ferroelectric memory cells. More particularly, the invention is related to ferroelectric memory cells wherein the ferroelectric capacitor is positioned directly on top of a contact plug. The bottom electrode stack is prepared by depositing a ferroelectric film atop an Ir or Ru metal electrode layer, then annealing the ferroelectric layer in an oxygen ambient wherein the partial pressure of oxygen is controlled at a level sufficient to oxidize the ferroelectric layer but not at a level sufficient to oxidize the metal electrode layer.

Abstract: Dielectric material compositions comprising HfO2 and a second compound are disclosed. The compositions are characterized by at least a part of the compositions being in a cubic crystallographic phase. Further, semiconductor based devices comprising such dielectric material compound and method for forming such compounds are disclosed.

Abstract: A method and system for evaluating the current-voltage characteristics of devices where negative resistance behavior is observed. More particularly the present invention relates to a method and system for evaluating accurately the electrical overstress or ESD performance of semiconductor devices during the voltage transition region (positive to negative). The method comprises applying a signal comprising at least two amplitudes within the pulse. By suitably adjusting the amplitude of the first level, such that it is high enough to trigger the device-under-test, and subsequently applying one or more levels within the same signal while keeping the device-under-test in the on-state, the device IV characteristics can be comprehensively extracted, without being limited by the system loadline.

Abstract: Method and apparatus to obtain as-deposited polycrystalline and low-stress SiGe layers. These layers may be used in Micro Electro-Mechanical Systems (MEMS) devices or micromachined structures. Different parameters are analysed which effect the stress in a polycrystalline layer. The parameters include, without limitation: deposition temperature; concentration of semiconductors (e.g., the concentration of Silicon and Germanium in a SixGe1?x layer, with x being the concentration parameter); concentration of dopants (e.g., the concentration of Boron or Phosphorous); amount of pressure; and use of plasma. Depending on the particular environment in which the polycrystalline SiGe is grown, different values of parameters may be used.

Abstract: A charge pump circuit and method for supplying power. The charge pump circuit includes a first circuit receiving at least one low voltage signal and generating an output voltage signal. The charge pump circuit also includes a second circuit receiving a clock signal and the output voltage signal. The second circuit sends a request signal based on a comparison of the output voltage signal with two reference voltage signals, where the two reference voltage signals are derived from two supply voltage signals having a substantially constant potential difference. The charge pump circuit further includes a high voltage generator receiving the request signal and sending the two supply voltage signals to the first circuit and the second circuit. The high voltage generator adjusts the voltage potentials of the two supply voltage signals such that the voltage potential of the output voltage signal falls between the voltage potentials of the two reference voltage signals.

Abstract: The present invention discloses a method for forming germanides on substrates with exposed germanium and exposed dielectric(s) topography, thereby allowing for variations in the germanide forming process. The method comprises the steps of depositing nickel on a substrate having topography, performing a first thermal step to convert substantially all deposited nickel in regions away from the topography into a germanide, selectively removing the unreacted nickel, and performing a second thermal step to lower the resistance of formed germanide.

Abstract: A MOSFET comprising a fully germano-silicided gate electrode having a high work function is disclosed. This gate electrode is formed by a self-aligned reaction process between a silicidation metal and a semiconductor material comprising silicon and germanium. Preferably, the fully germano-silicided gate is formed by a reaction between nickel and SiGe. The work function of the fully germano-silicided gate electrode can be tuned.

Abstract: Methods and systems are described for improving optical lithographic processing of a substrate by selecting appropriate system parameters in order to obtain a good image or print of the pattern to be obtained in a resist layer, which includes selecting a set of system parameters for an optical lithographic system having selectable system parameters, thus characterising the optical lithographic system and obtaining transferred lens pupil information. The latter is performed by obtaining, for each point of a set of points within a lens pupil of the optical lithographic system with the selected set of system parameters, a value of at least one optical parameter at a level of the substrate, the at least one optical parameter being a property of a light ray projected towards the substrate from the point of the set of points within the lens pupil. The lens pupil information then is combined with information about the mask to be used for generating the pattern in the resist layer.

Abstract: The present invention provides a system for the release of neurotransmitters and a method for the manufacturing of such a system. The system according to the present invention allows for local release of neurotransmitters and therefore makes it possible to activate single neurons. Furthermore, the system according to the invention is efficient, reproducible, and has a low power supply.

Abstract: A method for manufacturing a MOSFET device with a fully silicided (FUSI) gate is described. This method may be used to prevent formation of shorts between the FUSI gate and a contact to a source and/or a drain region. In particular, the method discloses the formation of an expansion volume above a gate dielectric. The volume is designed to substantially contain the fully silicided gate.

Abstract: The present invention is related to a composition comprising an oxidizing compound and a complexing compound with the chemical formula wherein R1, R2, R3 and R4 are selected from the group consisting of H and any organic side chain. The oxidizing compound can be in the form of an aqueous solution. The complexing compound is for complexing metal ions. Metal ions can be present in the solution or in an external medium being contacted with the solution.

Abstract: Methods of providing a semiconductor device with a control electrode structure having a controlled overlap between control electrode and first and second main electrode extensions without many spacers are disclosed. A preferred method provides a step of etching back an insulating layer performed after amorphizing and implanting the main electrode extensions. Preferably, the step that amorphizes the extensions also partly amorphizes the insulating layer. Because etch rates of amorphous insulator and crystalline insulator differ, the amorphized portion of the insulating layer may serve as a natural etch stop to enable even better fine-tuning of the overlap. Corresponding semiconductor devices are also provided.