Abstract: The present disclosure relates to methods and solutions for growing metal charge-transfer salts on a metal surface, such as a metal layer at the bottom of a via hole. The method makes use of a solution comprising a salt additive. The temperature during growth is in the range of ?100° C. to +100° C. The method allows controlled growth of the metal charge transfer salt inside via hole while limiting growth outside the via hole. The method further limits corrosion of the metallic connections at the bottom of the via hole.

Abstract: An electrostatic discharge (ESD) protection circuit for the protection of an electronic circuit from an ESD event. The electronic circuit, in operation, is provided with a supply voltage and a reference voltage (typically electrical ground) via voltage terminals and/or power supply buses. The protection circuit includes two bipolar transistors in series, where the transistors are coupled between the supply voltage terminal/bus and the reference voltage terminal/bus. The bases of the transistors are coupled via a connection including two resistors in series, where the connection point between the two resistors is coupled with the connection point between the two transistors.

Abstract: A semiconductor device is disclosed. In one aspect, the device comprises a channel area, the channel area comprising a channel layer in which charge carriers can move when the transistor is turned on, in order to pass a current through the transistor. The device further comprises a source area and a drain area contacting the channel layer for providing current to and from the channel layer. The method further comprises a gate electrode, preferably provided with a gate dielectric between the gate electrode and the channel layer. The channel layer may comprise a III-V material, and the source and drain areas comprise SiGe, being SixGe1-x, with x between 0 and 100%, arranged so that heterojunctions are present between III-V material and SiGe, wherein the heterojunctions are oriented so as to intersect with the gate dielectric or the gate electrode.

Abstract: The present invention provides an impurity measuring method comprising the steps of dropping a drop of a first solution on the surface of a substrate to be measured, moving the drop dropped on the surface of the substrate so that the drop is kept in contact with the surface and collects an impurity absorbed on the surface, recovering the drop after the movement and analyzing the recovered drop by chemical analysis to determine the type and concentration of the impurity, characterized in that the first solution is phobic to the substrate and the substrate consists substantially of Ge. The method is of particular importance for measuring metallic contamination on the surface of Ge substrates.

Abstract: A method for forming deep trench or via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), depositing spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to narrow the opening, removing through said narrowed opening the remaining part of the sacrificial material (e.g. by isotropic etching) and finally sealing the opening of the airgap by depositing a conformal layer (TEOS) above the spacers. The method of forming an airgap is demonstrated successfully for use as deep trench isolation structures in BiCMOS devices.

Abstract: An electronic device and a process for manufacturing the same are disclosed. In one aspect, the device comprises an electrode comprising a metal compound selected from the group of tantalum carbide, tantalum carbonitride, hafnium carbide and hafnium carbonitride. The device further comprises a high-k dielectric layer of a hafnium oxide comprising nitrogen and silicon, the high-k dielectric layer having a k value of at least 4.0. The device further comprises a nitrogen and/or silicon and/or carbon barrier layer placed between the electrode and the high-k dielectric layer. The nitrogen and/or silicon and/or carbon barrier layer comprises one or more metal oxides, the metal of the metal oxides being selected from the group of lanthanides, aluminium or hafnium.

Abstract: A new, effective and cost-efficient method of introducing Fluorine into Hf-based dielectric gate stacks of planar or multi-gate devices (MuGFET), resulting in a significant improvement in both Negative and Positive Bias Temperature Instabilities (NBTI and PBTI) is provided. The new method uses an SF6 based metal gate etch chemistry for the introduction of Fluorine, which after a thermal budget within the standard process flow, results in excellent F passivation of the interfaces. A key advantage of the method is that it uses the metal gate etch for F introduction, requiring no extra implantations or treatments. In addition to the significant BTI improvement with the novel method, a better Vth control and increased drive current on MuGFET devices is achieved.

Abstract: A method is disclosed for bonding two elements by means of a bonding agent such as a glue layer, wherein the bonding agent is removable, and wherein between the bonding agent and at least one element, a sacrificial layer is applied which is selectively removable with respect to that element. According to embodiments, the elements comprise a die or a substrate bonded to a carrier wafer. The nature and type of the die or substrate and of the carrier can vary within the scope of embodiments of the invention. Also disclosed is a composite substrate obtainable by methods of the invention.

Abstract: A method for forming deep trench or via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), depositing spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to narrow the opening, removing through said narrowed opening the remaining part of the sacrificial material (e.g. by isotropic etching) and finally sealing the opening of the airgap by depositing a conformal layer (TEOS) above the spacers. The method of forming an airgap is demonstrated successfully for use as deep trench isolation structures in BiCMOS devices.

Abstract: A thickness shear mode (TSM) resonator is described, comprising a diamond layer. The diamond layer is preferably a high quality diamond layer with at least 90% sp3 bonding or diamond bonding. A method for manufacturing such a resonator is also described. The thickness shear mode resonator according to embodiments described herein may advantageously be used in biosensor application and in electrochemistry applications.

Abstract: An interconnect module and a method of manufacturing the same. The method of making an interconnect module on a substrate comprises forming an interconnect section on the substrate. The interconnect section comprises at least two metal interconnect layers separated by a dielectric layer. The method further comprises forming a passive device on the substrate at a location laterally adjacent to the interconnect section. The passive device comprises at least one moveable element comprising a metal layer. The method further comprises forming the metal layer and one of the at least two metal interconnect layers from substantially the same material.

Abstract: The present invention relates to a method for the patterning of a stack of layers on a surface with high topography. A method of the present invention can be used for gate patterning for multiple Gate FETs (MuGFETs), for patterning of the control gate in non-volatile memory applications, and for the patterning of the poly emitter in BiCMOS devices. The present invention also relates to a device prepared by a method of the invention.

Abstract: A method of producing a semiconductor device using a selective epitaxial growth (SEG) process is disclosed. In one aspect, the method comprises providing a semiconductor substrate, forming a pattern of an insulation material on the semiconductor substrate, thereby defining a covered and non covered surface, performing a cleaning processing of the covered and non covered surface of the substrate having the insulating pattern defined, loading the substrate with the insulating pattern into a reaction chamber of an epitaxial reactor, and starting a selective epitaxial growth comprising an injection of at least one semiconductor source gas possibly with at least one first carrier gas in the reaction chamber of the epitaxial reactor. The method further comprises, prior to the selective epitaxial growth, the surface of the substrate is subjected in the reaction chamber to an in situ pre-treatment with the injection of a halogen containing etching gas possibly with a second carrier gas.

Abstract: A method is provided for the patterning of a stack comprising elements that do not form volatile compounds during conventional reactive ion etching. More specifically the element(s) are Lanthanide elements such as Ytterbium (Yb) and the patterning preferably relates to the dry etching of silicon and/or germanium comprising structures (e.g. gates) doped with a Lanthanide e.g. Ytterbium (Yb doped gates). In case the silicon and/or germanium comprising structure is a gate electrode the silicon and/or germanium is doped with a Lanthanide (e.g. Yb) for modeling the work function of a gate electrode.

Abstract: A method is described for extracting the spatial distribution of charge stored in a charge-trapping layer of a semiconductor device. The method comprises the steps of performing a first charge-pumping measurement on a device under test using a variation of the upper level of the pulse and performing a second charge-pumping measurement on this device using a variation of the lower level of the pulse. The data obtained is combined for extracting the spatial distribution. This is done by establishing a relation between a charge pumping current Icp and a calculated channel length Lcalc of the semiconductor device by reconstructing spatial charge distribution estimates from the charge pumping curves for multiple values of the charge pumping current Icp.

Abstract: A semiconductor device is provided comprising a main electrode (4) and a dielectric (3) in contact with the main electrode (4), the main electrode (4) comprising a material having a work function and a work function modulating element (6) for modulating the work function of the material of the main electrode (4) towards a predetermined value. The main electrode (4) furthermore comprises a diffusion preventing dopant element (5) for preventing diffusion of the work function modulating element (6) towards and/or into the dielectric (3). Methods for forming such a semiconductor device are also described.

Abstract: A hardware memory architecture or arrangement suited for multi-processor systems or arrays is disclosed. In one aspect, the memory arrangement includes at least one memory queue between a functional unit (e.g., computation unit) and at least one memory device, which the functional unit accesses (for write and/or read access).

Abstract: Manufacturing a semiconductor device involves forming (200) a sacrificial layer where a micro cavity is to be located, forming (210) a metal layer of thickness greater than 1 micron over the sacrificial layer, forming (220) a porous layer from the metal layer, the porous layer having pores of length greater than ten times their breadth, and having a breadth in the range 10 nm-500 nanometers. The pores can be created by anodising, electrodeposition or dealloying. Then the sacrificial layer can be removed (230) through the porous layer, to form the micro cavity, and pores can be sealed (240). Encapsulating MEMS devices with a porous layer can reduce costs by avoiding using photolithography for shaping the access holes since the sacrificial layer is removed through the porous membrane.

Abstract: The present invention discloses an improved method for detecting an analyte. The present invention may be used for sensing devices which have a higher sensitivity and which can be used to detect very low concentration of analyte. In one embodiment, the method comprises the steps of providing a substrate, said substrate comprising a conductive region and a recognition layer, said conductive region having at least a first surface and a second surface, wherein said first surface is operatively associated with said recognition layer; subjecting said substrate to said analyte such that an interaction occurs between said analyte and said recognition layer; directing radiation through said substrate such that said radiation incidents on said conductive region and said recognition layer; and measuring the intensity of said radiation absorbed or transmitted by said substrate as a function of the wavelength in order to determine the presence of an analyte.

Abstract: A method for the production of a photovoltaic device is disclosed. In one aspect, the method comprises providing a carrier substrate. The method further comprises forming a crystalline semiconductor layer on the substrate. The method further comprises carrying out hydrogen passivation of the crystalline semiconductor layer. The method further comprises creating an emitter on the surface of the passivated crystalline semiconductor layer.