Abstract: A technique is described for the preparation of polymers according to a process in which the starting compound of formula (I) is polymerized in the presence of a base in an organic solvent. No end chain controlling agents are required during the polymerization to obtain soluble precursor polymers. The precursor polymer such obtained comprises structural units of the formula (II). In a next step, the precursor polymer (II) is subjected to a conversion reaction towards a soluble or insoluble conjugated polymer by thermal treatment. The arylene or heteroarylene polymer comprises structural units of the formula III. In this process the dithiocarbamate group acts as a leaving group and permits the formation of a precursor polymer of structural formula (II), which has an average molecular weight from 5000 to 1000000 Dalton and is soluble in common organic solvents.
Type:
Grant
Filed:
October 21, 2004
Date of Patent:
August 21, 2007
Assignees:
Interuniversitair Microelektronica Centrum (IMEC), Limburgs Universitair Centrum
Abstract: A method of bonding two elements such as wafers used in microelectronics applications is disclosed. One inventive aspect relates to a method for bonding comprising producing on a first main surface of a first element a first solder ball, producing on a first main surface of a second element a second solder ball, providing contact between the first solder ball and the second solder ball, bonding the first element and the second element by applying a reflow act whereby the solder balls melt and form a joined solder ball structure. Prior to the bonding, the first solder ball is laterally embedded in a nonconductive material, such that the upper part of the first solder ball is not covered by the non-conductive material. Devices related to such methods are also disclosed.
Type:
Application
Filed:
April 16, 2007
Publication date:
August 9, 2007
Applicant:
INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC)
Inventors:
Walter DeRaedt, Steven Brebels, Steven Sanders, Tom Torfs, Eric Beyne
Abstract: A method for providing an optical interface with at least one optical coupling structure for a packaged optical device is described. The at least one optical coupling structure may be, for example, wave-guides and/or microlenses. The packaged optical device includes an external alignment structure. The external alignment structure has a support means with at least one hole and at least one alignment feature. The method includes providing optical encapsulate material in the hole of the support means. Optical coupling structures, such as wave-guides or microlenses, may be provided into the encapsulation at a well-defined position relative to the at least one alignment feature of the external alignment structure. By providing the optical coupling structures directly in the material comprised in the encapsulation, a high degree of alignment accuracy is obtained.
Type:
Grant
Filed:
July 14, 2005
Date of Patent:
July 31, 2007
Assignee:
Interuniversitair Microelektronica Centrum (IMEC)
Abstract: A method for producing probes for atomic force microscopy comprises producing, on a surface of one side of a semiconductor substrate, one or more moulds for the production of one or more probe tips. One or more probe configurations and at least one set of a probe tip and a cantilever are also produced on the side of the substrate, wherein each configuration comprises a contact region for attachment of a holder. The surface area of each contact region is smaller in size than the surface area of the holder. The method further includes attaching one or more holders to the contact region(s), and releasing the probe configuration and the holder from the substrate by under-etching the probe configuration from the side of the substrate on which the probe configuration is produced.
Type:
Grant
Filed:
December 16, 2004
Date of Patent:
July 10, 2007
Assignee:
Interuniversitair Microelektronica Centrum vzw (IMEC)
Abstract: A method is provided for characterising an immersion lithography process of a device using an immersion liquid. In order to study pre-soak and post-soak effects on the image performance of an immersion lithography process, the method includes determining at least one image performance characteristic as function of contact times between the immersion liquid and the device for a device illuminated in a dry lithography process and contacted with said immersion liquid prior and/or after said illumination. Based on the image performance characteristic, a lithography process characteristic is derived for the immersion lithography process.
Type:
Application
Filed:
December 29, 2005
Publication date:
July 5, 2007
Applicant:
Interuniversitair Microelektronica Centrum (IMEC)
Abstract: This invention relates to a method for removing oxides from the surface of a Ge semiconductor substrate comprising the step of subjecting the surface to a Ge oxide etching solution characterized in that the Ge oxide etching solution removes Ge oxides and Ge sub-oxides from the surface.
Type:
Grant
Filed:
September 17, 2004
Date of Patent:
July 3, 2007
Assignee:
Interuniversitair Microelektronica Centrum (IMEC)
Abstract: The present invention provides a method for processing a semiconductor device wherein a dielectric layer is partially converted into a silicon-oxy-nitride by incorporation of nitrogen atoms into the dielectric layer, which comprises a silicon oxide. Before the introduction of the nitrogen atoms into the dielectric layer, the dielectric layer is provided as a silicon oxide in which the atomic silicon to oxygen ration is greater than ½. In this way, MOS transistors are obtained with a high quality interface between the dielectric region and semiconductor substrate, and a dielectric region which is impermeable to impurity atoms from the gate region and which has a thickness which is substantially equal to the dielectric layer as deposited.
Type:
Grant
Filed:
October 15, 2004
Date of Patent:
July 3, 2007
Assignees:
Interuniversitair Microelektronika Centrum (IMEC), Koninklijke Philips Electronics N.V.
Inventors:
Vincent Charles Venezia, Florence Nathalie Cubaynes
Abstract: A method is described for closing openings in a film, for example, in microelectronic process technology, whereby substantially no deposition material passes through the openings, which can be important if fragile micro devices are positioned under the openings. The closure of these openings can cause an underlying cavity to be hermetically sealed, in which an object can be located. In particular the method provides a way for hermetically sealing cavities under controlled atmosphere and pressure in the encapsulation and sealing processes of cavities comprising fragile content. The cavities may comprise for example Micro Electro Mechanical Systems (MEMS).
Type:
Grant
Filed:
December 22, 2003
Date of Patent:
June 26, 2007
Assignee:
Interuniversitair Microelektronica Centrum (IMEC)
Abstract: A piezoelectric bimorph cantilever is used for determining physical parameters in a gaseous or liquid environment. The sensor works as a driven and damped oscillator. Contrary to common cantilever sensor systems, the piezoelectric film of the bimorph cantilever acts as both a sensor and an actuator. Using at least two resonance mode of the bimorph cantilever, at least two physical parameters can be measured simultaneously in a gas or a liquid. An optimized piezoelectric cantilever and a method to produce the cantilever are also described.
Type:
Application
Filed:
December 14, 2006
Publication date:
June 21, 2007
Applicants:
INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC), UNIVERSITEIT HASSELT
Abstract: The invention relates to a method for fabricating a semiconductor device having a semiconductor body that comprises a first semiconductor structure having a dielectric layer and a first conductor, and a second semiconductor structure having a dielectric layer and a second conductor, that part of the first conductor which adjoins the dielectric layer having a work function different from the work function of the corresponding part of the second conductor. In one embodiment of the invention, after the dielectric layer has been applied to the semiconductor body, a metal layer is applied to the said dielectric layer, and then a silicon layer is deposited on the metal layer and is brought into reaction with the metal layer at the location of the first semiconductor structure, forming a metal silicide.
Type:
Grant
Filed:
October 18, 2004
Date of Patent:
June 5, 2007
Assignees:
Interuniversitair Microelektronica Centrum (IMEC), Koninklijke Philips Electronics N.V.
Inventors:
Tom Schram, Jacob Christopher Hooker, Marcus Johannes Henricus van Dal
Abstract: The present invention is related to a front-end circuit for an optical communication system including a laser module arranged for transmitting bursts of data signals over an optical network and a driving circuit for providing the bursts of data signals to the laser module. The front-end circuit further includes receiver means in connection with said laser module and arranged for receiving from the optical network optical echo signals. The laser module includes a laser diode arranged for transmitting the bursts of data signals. The driving circuit is arranged for setting a disabling signal for stopping the laser diode from transmitting bursts of the data signals. Fiber-related information can be extracted from the echo signals, such as distance-resolved optical fiber reflections and fiber attenuation.
Type:
Application
Filed:
October 4, 2006
Publication date:
May 31, 2007
Applicants:
Interuniversitair Microelektronica Centrum (IMEC), Universiteit Gent (University Ghent)
Inventors:
Jan Vandewege, Bert Mulder, Wei Chen, Xing Qui
Abstract: A method and apparatus for immersion lithography is described. The method includes positioning a semiconductor substrate under an optical immersion head assembly, providing an immersion liquid between the substrate and the optical immersion head assembly, and supplying a tensio-active gaseous substance along the perimeter of the contact area of the immersion liquid and the substrate. The immersion liquid contacts at least an area of the substrate. The tensio-active gaseous substance is chosen such that, when at least partially mixed with the immersion liquid, the mixture has a lower surface tension than the immersion liquid, thereby creating a surface tension gradient pulling the immersion liquid from the perimeter towards an inside portion of the contact area.
Type:
Grant
Filed:
July 1, 2005
Date of Patent:
May 29, 2007
Assignee:
Interuniversitair Microelektronica Centrum (IMEC)
Abstract: A metal nanostructure is described. Such a metal nanostructure may comprise a nanometric metal core comprising gold, silver or an assembly or alloy of gold and silver, and one or more molecules attached to one or more surfaces of the nanometric metal core, where each of the molecules has the structural formula W-X-Y-Z, where W is an atom or a chemical group bound to the nanometric metal core, X is a hydrophobic spacer, Y is a hydrophilic spacer and Z is either hydrogen or a reactive group able to bind a reactive substrate or biomolecule. Such a metal nanostructure may be useful in making pharmaceutical compositions.
Type:
Application
Filed:
June 30, 2006
Publication date:
May 24, 2007
Applicant:
Interuniversitair Microelektronica Centrum (IMEC)
Abstract: The present invention is related to a method for controlled transport of magnetic beads between a position X and different position Y, such that the magnetic beads are manipulated or transported by applying successively a series of N local magnetic fields which have magnetic field gradients different from 0 in the neighborhood of said magnetic beads. Each of these N local magnetic fields is generated by a single current carrying structure, in which the current density is not constant. The invention generally relates to application in the domain of biochips and micro-arrays, used in diagnostics, genetics and molecular studies.
Type:
Grant
Filed:
April 4, 2006
Date of Patent:
May 15, 2007
Assignee:
Interuniversitair Microelektronica Centrum (IMEC) vzw
Abstract: An aspect of the present invention provides a design environment in which a floorplan of a semiconductor device is optimised by taking into account activation or access frequency information to and from resources. Since segmented bus architecture is also a good alternative approach for the power consumption of the network, the floorplanning approach for energy optimization of the communicating network is adapted for such architectures in embodiments of the present invention. The provided method comprises both architecture optimizations as well as physical design optimizations.
Type:
Grant
Filed:
June 21, 2004
Date of Patent:
May 8, 2007
Assignee:
Interuniversitar Microelektronica Centrum (IMEC)
Inventors:
Antonis Papanikolaou, Hua Wang, Jin Guo, Miguel Miranda, Francky Catthoor
Abstract: Methods of forming semiconductor devices with a layered structure of thin and well defined layer of activated dopants, are disclosed. In a preferred method, a region in a semiconductor substrate is amorphized, after which the region is implanted with a first dopant at a first doping concentration. Then a solid phase epitaxy regrowth step is performed on a thin layer of desired thickness of the amorphized region, in order to activate the first dopant only in this thin layer. Subsequently, a second dopant is implanted in the remaining amorphous region at a second doping concentration. Subsequent annealing of the substrate activates the second dopant only in said remaining region, so a very abrupt transition between dopant characteristics of the thin layer with first dopant and the region with the second dopant is obtained.
Type:
Grant
Filed:
October 15, 2004
Date of Patent:
May 8, 2007
Assignees:
Interuniversitair Microelektronica Centrum (IMEC), Koninklijke Philips Electronics N.V.
Abstract: A method of bonding two elements such as wafers used in microelectronics applications is disclosed. One inventive aspect relates to a method for bonding comprising producing on a first main surface of a first element a first solder ball, producing on a first main surface of a second element a second solder ball, providing contact between the first solder ball and the second solder ball, bonding the first element and the second element by applying a reflow act whereby the solder balls melt and form a joined solder ball structure. Prior to the bonding, the first solder ball is laterally embedded in a nonconductive material, such that the upper part of the first solder ball is not covered by the non-conductive material. Devices related to such methods are also disclosed.
Type:
Grant
Filed:
June 30, 2005
Date of Patent:
April 17, 2007
Assignee:
Interuniversitair Microelektronica Centrum (IMEC)
Inventors:
Walter De Raedt, Steven Brebels, Steven Sanders, Tom Torfs, Eric Beyne
Abstract: A method is described for forming an at least partially silicided contact. In one embodiment, a hardmask is deposited over a contact. A coating of sacrificial material is then provided on top of the hardmask. The sacrificial material coating is etched back until the top of the contact is exposed. The contact is then opened, the sacrificial material is removed, and a silicidation of the contact is performed.
Type:
Application
Filed:
October 7, 2005
Publication date:
April 12, 2007
Applicants:
Interuniversitair Microlektronica Centrum (IMEC), Texas Instruments Inc.
Abstract: A multiple gate semiconductor device. The device includes at least two gates. The dopant distribution in the semiconductor body of the device varies from a low value near the surface of the body towards a higher value inside the body of the device.
Type:
Grant
Filed:
July 16, 2004
Date of Patent:
April 10, 2007
Assignee:
Interuniversitair Microelektronica Centrum (IMEC vzw)