Patents Assigned to IMEC
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Patent number: 10515855Abstract: At least one embodiment relates to a method for integrating Si1-xGex structures with Si1-x?Gex? structures in a semiconductor device. The method includes providing a device that includes a plurality of Si1-xGex structures, where 0?x<1. The method also includes depositing a layer of GeO2 on a subset of the Si1-xGex structures. Further, the method includes heating at least the subset of Si1-xGex structures at a temperature high enough and for a time long enough to transform the subset of Si1-xGex structures into a subset of Si1-x?Gex? structures with x?>x.Type: GrantFiled: March 6, 2018Date of Patent: December 24, 2019Assignee: IMEC VZWInventor: Kurt Wostyn
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Patent number: 10514333Abstract: The present disclosure describes a device for measuring an optical absorption property of a fluid as function of wavelength. The device comprises a broadband light source for emitting light, a plurality of integrated optical waveguides for guiding this light and a light coupler for coupling the emitted light into the integrated optical waveguides such that the light coupled into each integrated optical waveguide has substantially the same spectral distribution. The device also comprises a microfluidic channel for containing the fluid, arranged such as to allow an interaction of the light propagating through each waveguide with the fluid in the microfluidic channel, and a plurality of spectral analysis devices optically coupled to corresponding waveguides—such as to receive the light after interaction with the fluid. The spectral analysis devices are adapted for generating a signal representative of a plurality of spectral components of the light.Type: GrantFiled: June 30, 2016Date of Patent: December 24, 2019Assignee: IMEC VZWInventor: Xavier Rottenberg
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Patent number: 10516423Abstract: A polar transmitter provided for transmitting a phase/frequency modulated and amplitude modulated transmit signal and a method for generating a transmit signal using a polar transmitter are described. An example polar transmitter comprises a phase locked loop for generating a phase/frequency modulated precursor of the transmit signal. The phase locked loop comprises at its input a phase error detection unit for detecting a phase error of the precursor fed back from the output of the phase locked loop to the phase error detection unit as a feedback signal. The polar transmitter comprises a digital amplitude modulator for amplitude modulation of the precursor, resulting in the transmit signal. The digital amplitude modulator is arranged within the phase locked loop for amplitude modulation of the precursor before being output by the PLL. The phase error detection unit is further provided for detecting the amplitude of the feedback signal.Type: GrantFiled: June 13, 2017Date of Patent: December 24, 2019Assignees: IMEC VZW, VRIJE UNIVERSITEIT BRUSSELInventors: Nereo Markulic, Jan Craninckx
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Patent number: 10510774Abstract: An integrated circuit (IC) power distribution network is disclosed. In one aspect, the IC includes a stack of layers formed on a substrate. The IC includes standard cells with parallel gate structures oriented in a direction y. Each cell includes an internal power pin for supplying a reference voltage to the cell. The stack includes metal layers in which lines are formed to route signals between cells. The lines in each metal layer have a preferred orientation that is orthogonal to that of the lines in an adjacent metal layer. A first layer is the lowest metal layer that has y as a preferred orientation while also providing routing resources for signal routing between the cells. A second layer is the nearest metal layer above this first layer. The IC includes a power distribution network for delivering the reference voltage to the power pin.Type: GrantFiled: April 5, 2017Date of Patent: December 17, 2019Assignee: IMEC vzwInventors: Peter Debacker, Praveen Raghavan, Vassilios Constantinos Gerousis
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Patent number: 10506537Abstract: Example embodiments relate to transceiver devices with real-time clocks. One embodiment includes a transceiver device. The transceiver device includes a real-time clock arranged for providing a clock signal. The transceiver device also includes a receiving section. The receiving section includes a main receiver arranged for receiving communication signals. The receiving section also includes a wake-up receiver. The wake-up receiver is arranged for receiving a calibration signal that includes clock timing information containing a time stamp. The wake-up receiver is also arranged for adjusting the real-time clock based on the clock timing information.Type: GrantFiled: December 4, 2018Date of Patent: December 10, 2019Assignee: Stichting IMEC NederlandInventor: Yao-Hong Liu
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Patent number: 10504951Abstract: Example embodiments relate to image sensors and imaging apparatuses. One embodiment includes an image sensor for acquiring an image of an object. The image sensor includes an array of photo-sensitive areas formed on a substrate. Each photo-sensitive area is a continuous area within the substrate and is configured to detect incident light. The image sensor also includes an array of interference filters. Each inference filter is configured to selectively transmit a wavelength band. The array of interference filters is monolithically integrated on the array of photo-sensitive areas. A plurality of the interference filers is associated with a single photo-sensitive area of the array of photo-sensitive areas. Each interference filter in the plurality of interference filters is configured to selectively transmit a unique wavelength band to the photo-sensitive area and each interference filter in the plurality of interference filters is associated with a respective portion of the single photo-sensitive area.Type: GrantFiled: August 10, 2018Date of Patent: December 10, 2019Assignee: IMEC VZWInventor: Bert Geelen
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Patent number: 10495666Abstract: A method of measuring an electrical characteristic of a current path is disclosed. In one aspect, the method includes a probe for scanning spreading resistance microscopy (SSRM), a test sample contacted by the probe, a back contact on the test sample, a bias voltage source and a logarithmic SSRM amplifier, when a modulation at a predefined frequency is applied to either the contact force of the probe or to the bias voltage, the device comprising electronic circuitry for producing in real time a signal representative of the electrical characteristic, according to the formula lognA=±VSSRM±logn(dV)+Vmultiplier.Type: GrantFiled: July 3, 2018Date of Patent: December 3, 2019Assignee: IMEC vzwInventors: Kristof Paredis, Umberto Celano, Wilfried Vandervorst, Oberon Dixon-Luinenburg
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Patent number: 10495516Abstract: The invention relates to a multi-channel spectrometer device (10) for detecting/quantifying a predetermined analyte (5) in a medium (6). The device (10) comprises an input (11) for receiving radiation (7), a first plurality of optical modulators (12) adapted for transforming the radiation (7) in accordance with a first transfer function, and a second plurality of optical modulators (13) adapted for transforming the radiation (7) in accordance with a second transfer function. The spectrometer device also comprises a detector (15) for generating output signals (4) indicative for the intensity of each transformed radiation signal. The ratio of the number of optical modulators in the first plurality and the number of optical modulators in the second plurality is determined by the ratio of a reference spectrum of the predetermined analyte transformed by the first transfer function and the reference spectrum transformed by the second transfer function.Type: GrantFiled: June 28, 2016Date of Patent: December 3, 2019Assignee: IMEC VZWInventor: Xavier Rottenberg
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Patent number: 10493378Abstract: A method for producing a structure including, on a main surface of a substrate, at least one elongated cavity having openings at opposing ends. The method includes providing a substrate having a main surface. On the main surface, a first pair of features are formed that protrude perpendicularly from the main surface. The features have elongated sidewalls and a top surface, are parallel to one another, are separated by a gap having a width s1 and a bottom area, and have a width w1 and a height h1. At least the main surface of the substrate and the first pair of features are brought in contact with a liquid, suitable for making a contact angle of less than 90° with the material of the elongated sidewalls and subsequently the substrate is dried.Type: GrantFiled: August 10, 2017Date of Patent: December 3, 2019Assignee: IMEC VZWInventors: Zheng Tao, Boon Teik Chan, XiuMei Xu, Khashayar Babaei Gavan, Efrain Altamirano Sanchez
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Patent number: 10491224Abstract: The present disclosure describes systems and methods to provide a digital wakeup timer with reduced size and lower power. An example system or apparatus includes a wakeup timer employing a digital-intensive frequency-locked loop (DFLL) architecture to fully utilize the advantages of advanced CMOS processes. Such a system includes a bang-bang frequency detector, a digital loop filter, a digitally-controlled oscillator (DCO), and a multi-phase clock generator. An output of the bang-bang frequency detector is provided to an input of the digital loop filter. An output of the digital loop filter is provided to the DCO. An output of the DCO includes information indicative of an output frequency. The multi-phase clock generator provides respective clock signals based on the output frequency to the bang-bang frequency detector, the digital loop filter, and the DCO.Type: GrantFiled: February 20, 2019Date of Patent: November 26, 2019Assignees: Stichting IMEC Nederland, Technische Universiteit DelftInventors: Ming Ding, Zhihao Zhou, Yao-Hong Liu, Fabio Sebastiano
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Patent number: 10488732Abstract: Example embodiments relate to an electro-optical device that includes a vertical p-i-n diode waveguide. The electro-optical device includes a waveguide portion adapted for propagating a multimode wave, the waveguide portion including an intrinsic semiconductor region of the vertical p-i-n diode, a first contact and a second contact for electrically contacting a first electrode and a second electrode of the vertical p-i-n diode. The device also includes an input section for coupling radiation into the waveguide portion and an output section for coupling radiation out of the waveguide portion. The input section, the output section, and the waveguide portion are configured to support a multimode interference pattern for the multimode wave with an optical field with a lateral inhomogeneous spatial distribution in the waveguide portion including regions with higher optical field intensity and regions with lower optical field intensity. The second contact physically contacts the second electrode.Type: GrantFiled: December 18, 2018Date of Patent: November 26, 2019Assignees: IMEC VZW, UNIVERSITEIT GENTInventors: Ashwyn Srinivasan, Joris Van Campenhout
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Patent number: 10490738Abstract: In one aspect, a resistive switching memory device includes a first electrode and a second electrode having interposed therebetween a first inner region and a second inner region, where the first and second inner regions contacting each other. The first inner region includes one or more metal oxide layers and the second inner region consists of a plurality of layers, where each of the layers of the second inner region is an insulating, a semi-insulating or a semiconducting layer. The second inner region comprises one or more layers having a stoichiometric or off-stoichiometric composition of a material selected from the group consisting of SiGex, SiNx, AlOx, MgOx, AINx, HfOx, HfSiOx, ZrOx, ZrSiOx, GdAlOx, DyScOx, TaOx and combinations thereof. The second inner region comprises one or more silicon-containing layers, such that one of the one or more silicon-containing layers contacts the first inner region.Type: GrantFiled: June 16, 2017Date of Patent: November 26, 2019Assignee: IMEC vzwInventor: Bogdan Govoreanu
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Patent number: 10490442Abstract: An example embodiment may include a method for blocking one or more portions of one or more trenches during manufacture of a semiconductor structure. The method may include (i) providing a substrate comprising one or more trenches, and a dielectric material under the one or more trenches, (ii) providing a first overlayer on the substrate, thereby filling the one or more trenches, the first overlayer having a planar top surface, a top portion of the first overlayer, comprising the top surface, being etchable selectively with respect to a condensed photo-condensable metal oxide, (iii) covering a first area of the top surface, situated directly above the one or more portions and corresponding thereto, with a block pattern of the condensed photo-condensable metal oxide, thereby leaving a second area of the top surface, having at least another portion of at least one of the trenches thereunder, uncovered.Type: GrantFiled: February 23, 2018Date of Patent: November 26, 2019Assignee: IMEC VZWInventors: Boon Teik Chan, Ming Mao, Peter De Schepper, Michael Kocsis
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Patent number: 10484000Abstract: A SAR DAC architecture is disclosed. In one aspect, the SAR DAC architecture uses two parallel DACs for performing a comparison and feedback simultaneously. While one DAC executes a feedback step, the output of the other DAC is used as input for a comparator. For fast operation, the comparator performs the comparison with a reference voltage that has a positive or negative offset from a mid-scale value. The sign of the offset is determined by a previous comparison step. As a result, the same delay can be used for each DAC feedback and comparison, reducing the total conversion time to the time needed for N comparisons for an N-bit architecture, which is a reduction of almost a factor of 2 compared to the conventional SAR architecture.Type: GrantFiled: December 13, 2018Date of Patent: November 19, 2019Assignee: IMEC vzwInventors: Ewout Martens, Benjamin Hershberg, Jan Craninckx
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Patent number: 10481864Abstract: The present disclosure relates to a method for emotion-triggered capturing of audio and/or image data by an audio and/or image capturing device. The method includes receiving and analyzing a time-sequential set of data including first physiological data representing a first physiological parameter corresponding to a first person, a second physiological data representing a second physiological parameter corresponding to a second person, and voice audio data including a voice of at least one of the first and the second person, to determine whether a simultaneous change of emotional state of a first person and a second person occurs and transmitting a trigger signal to the capturing device. The present disclosure also relates to a corresponding apparatus and a system comprising the apparatus.Type: GrantFiled: September 27, 2017Date of Patent: November 19, 2019Assignee: Stichting IMEC NederlandInventors: Vojkan Mihajlovic, Stefano Stanzione, Ulf Grossekathoefer
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Patent number: 10481504Abstract: Examples herein are related to a method and apparatus for determining dimensions of features in a patterned layer of a chip produced on a semiconductor production wafer. The production of the patterned layer includes a lithography step and an etching step, where the lithographic mask applied for producing the patterned layer is provided with one or more asymmetric marks. The position of printed and etched mark features is sensitive to lithographic and etch parameters. Changes in these positions are measured by overlay measurements, i.e. the measurement of the change in position of one mark relative to another. The obtained ‘pseudo’ overlay data are fitted to a parametric model, while characteristic feature dimensions are measured on a test wafer. The inverted model allows determination of feature dimensions on a production wafer. Application of the method on two different layers allows determination of edge placement errors between features of the two layers.Type: GrantFiled: June 9, 2017Date of Patent: November 19, 2019Assignee: IMEC VZWInventors: Christopher Ausschnitt, Vincent Truffert
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Patent number: 10466100Abstract: Provided are a dual coupler device configured to receive lights of different polarization components, a spectrometer including the dual coupler device, and a non-invasive biometric sensor including the spectrometer. The dual coupler device may include, for example, a first coupler layer configured to receive a light of a first polarization component among incident lights. and a second coupler layer configured to receive a light of a second polarization component among the incident lights, wherein a polarization direction of the light of the first polarization component is perpendicular to a polarization direction of the light of the second polarization component. The first coupler layer and the second coupler layer may be spaced apart from each other and extended along a direction in which the light propagates in the first coupler layer and the second coupler layer.Type: GrantFiled: February 17, 2016Date of Patent: November 5, 2019Assignees: SAMSUNG ELECTRONICS CO., LTD., IMEC VZWInventors: Seongho Cho, Tom Claes, Dongho Kim
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Patent number: 10466419Abstract: An optical system and method for connecting two optical fibers is described in the present disclosure. An example optical system includes a first optical fiber embedded in an embedding material, the first optical fiber comprising side walls extending in a longitudinal direction in contact with the embedding material, a second, external, optical fiber, and a self-written waveguide in optical contact with the first and second optical fibers. Only a cross section perpendicular to the side walls of the first optical fiber is outside the embedding material, in contact with the self-written waveguide.Type: GrantFiled: July 21, 2017Date of Patent: November 5, 2019Assignees: COMS&SENS, IMEC VZW, UNIVERSITEIT GENTInventors: Jeroen Missinne, Geert Van Steenberge, Geert Luyckx, Eli Voet
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Patent number: 10468483Abstract: The present disclosure relates to a method of forming a semiconductor device comprising horizontal nanowires. The method comprises depositing a multilayer stack on a substrate, the multilayer stack comprising first sacrificial layers alternated with layers of nanowire material; forming at least one fin in the multilayer stack; applying an additional sacrificial layer around the fin such that a resulting sacrificial layer is formed all around the nanowire material; and forming a nanowire spacer, starting from the resulting sacrificial layer, around the nanowire material at an extremity of the nanowire material. The present disclosure also relates to a corresponding semiconductor device.Type: GrantFiled: November 27, 2017Date of Patent: November 5, 2019Assignee: IMEC VZWInventors: Kurt Wostyn, Hans Mertens
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Patent number: 10469083Abstract: A device and a method for implementing a physically unclonable function is disclosed. In one aspect, the device includes at least one electronic structure including a dielectric. A conductive path is formed at a random position through the dielectric due to an electrical breakdown of the dielectric, or the electronic structure is adapted for generating an electrical breakdown of the dielectric such that the conductive path is formed through the dielectric at a random position. The at least one electronic structure is adapted for determining a distinct value of a set comprising at least two predetermined values. The distinct value is determined by the position of the conductive path through the dielectric.Type: GrantFiled: July 7, 2017Date of Patent: November 5, 2019Assignees: IMEC vzw, Katholieke Universiteit LeuvenInventors: Erik Bury, Jacopo Franco, Geert Hellings, Robin Degraeve, Benjamin Kaczer