Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes: providing a monocrystalline substrate having an upper surface covered with a masking layer comprising at least one opening exposing the upper surface; filling the opening by epitaxially growing therein a first layer comprising a first Group III-nitride compound; and growing the first layer further above the opening and on the masking layer by epitaxial lateral overgrowth, wherein the at least one opening has a top surface defined by three or more straight edges forming a polygon parallel to the upper surface and oriented in such a way with respect to the crystal lattice of the monocrystalline substrate so as to permit the epitaxial lateral overgrowth of the first layer in a direction perpendicular to at least one of the edges, thereby forming the semiconductor structure as an elongated structure.

Abstract: The disclosure relates to a logic circuit. The logic circuit comprises a first thin film transistor, TFT, having a gate connected to an input of the logic circuit, and a drain connected to an output of the logic circuit. The logic circuit further comprises a second TFT having a source connected to the output of the logic circuit. The logic circuit further comprises a third TFT having a gate connected to the input of the logic circuit, a source connected to the source of the second TFT, and a drain connected to a gate of the second TFT. The logic circuit further comprises a fourth TFT having a gate connected to the output of the logic circuit, and a source connected to the gate of the second TFT and the drain of the third TFT.

Abstract: According to a first aspect, there is provided a method of holographic wavefront sensing, the method including: receiving a light beam, which has a wavefront to be analyzed, on a transparent, flat substrate, which is provided with a lattice of opaque dots, wherein the substrate is arranged above an image sensor; detecting by the image sensor an interference pattern formed by diffracted light, being scattered by the opaque dots, and undiffracted light of the light beam received by the image sensor; processing the detected interference pattern to digitally reconstruct a representation of a displaced lattice of opaque dots, which would form the interference pattern on the image sensor upon receiving the light with a known wavefront; and comparing the representation of the displaced lattice to a known representation of the lattice of opaque dots on the substrate to determine a representation of the wavefront form of the received light beam.

Abstract: Devices and systems described herein relate to a sensing device that includes an output area and an electrode area. The output area includes an output circuit comprising an integrator adapted to integrate a received current so as to generate an output voltage corresponding to the received current. The electrode area includes an electrode comprising an exposed, electrically conductive, surface area and electrode circuitry connected to the exposed surface area. The electrode circuitry comprises a voltage-to-current transducer adapted to produce a wire current corresponding to a voltage present at the exposed surface area. The sensing device also includes a connecting wire electrically connecting the electrode circuitry to the output circuit, wherein the current received by the output circuit is the wire current.

Abstract: An integrated circuit for an imaging system is disclosed. In one aspect, an integrated circuit has an array of optical sensors, an array of optical filters integrated with the sensors and configured to pass a band of wavelengths onto one or more of the sensors, and read out circuitry to read out pixel values from the sensors to represent an image. Different ones of the optical filters are configured to have a different thickness, to pass different bands of wavelengths by means of interference, and to allow detection of a spectrum of wavelengths. The read out circuitry can enable multiple pixels under one optical filter to be read out in parallel. The thicknesses may vary non-monotonically across the array. The read out, or later image processing, may involve selection or interpolation between wavelengths, to carry out spectral sampling or shifting, to compensate for thickness errors.

Abstract: The present invention relates to a composition comprising one or more perovskite precursors dissolved in a mixture of solvents comprising: i. one or more polar aprotic solvents, each selected in such a way that it can, when used in absence of other components, dissolve said one or more perovskite precursors, ii. one or more linear alcohols of general formula CnH2n+1OH, wherein n is from 1 to 12, and iii. optionally, one or more acids wherein the polar aprotic solvent or mixture of polar aprotic solvents represent between 50 and 95 vol % of the mixture of solvents, wherein the vol % of the mixture of solvents not occupied by polar aprotic solvents is occupied for at least 90 vol %, preferably for 100 vol %, by the one or more linear alcohols, and the one or more acids if present.

Abstract: The disclosed technology relates generally to semiconductor devices, and more particularly to field-effect transistors (FETs) comprising nanostructures, such as nanowires, fins, and two dimensional materials. In an aspect, a FET device comprises a substrate having an insulating surface and a vertical structure extending in a direction substantially perpendicular to the insulating surface, where the vertical structure has at least outer surfaces formed of an insulating material. The FET device additionally includes a thin layer of two-dimensional (2D) material enveloping the vertical structure and at least part of the insulating surface. The FET device additionally includes two electrodes in electrical contact with the thin layer of 2D material, where one of the electrodes is formed on top of the vertical structure.

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate structure for a semiconductor device, and to methods of forming the same. In an aspect a method for forming a gate structure includes forming a first set of one or more semiconductor features and a second set of one or more semiconductor features. The method additionally includes forming a sacrificial gate extending across the semiconductor features of the first set and the semiconductor features of the second set.

Abstract: An example embodiment may include a sensor for monitoring and/or measuring stress in a semiconductor component. The component may include a substrate formed of a semiconductor material. The substrate may include a planar main surface. The sensor may include at least one slanted surface of the substrate material, the slanted surface being defined by an oblique inclination angle with respect to the main surface of the substrate. The sensor may also include at least one straight resistive path extending on at least part of the slanted surface and a plurality of contacts and terminals for accessing the at least one resistive path. The contacts and terminals may allow for the measurement of an electrical resistance of the resistive path and an assessment of a shear stress in a plane that is not parallel to the main surface of the substrate.

Abstract: Example embodiments relate to methods for forming source/drain contacts. One embodiment includes a method for forming a source contact and a drain contact in a semiconductor structure. The method includes providing a semiconductor structure that includes a semiconductor active area having channel, source, and drain regions, a gate structure on the channel region, a gate plug on the gate structure, spacers lining side walls of the gate structure and of the gate plug, an etch stop layer covering the source and gain regions, a sacrificial material on the etch stop layer over the source and drain regions, and a masking structure that masks the source and drain regions. The method also includes forming gaps, removing the masking structure, filling the gaps, exposing the sacrificial material, removing the sacrificial material, removing the etch stop layer, and forming the source contact and the drain contact by depositing a conductive material.

Abstract: A photonic integrated circuit comprises an input interface adapted for receiving an optical input signal and splitting it into two distinct polarization modes and furthermore adapted for rotating the polarization of one of the modes for providing the splitted signals in a common polarization mode,. The PIC also comprises a combiner adapted for combining the first mode signal and the second mode signal into a combined signal and a decohering means adapted for transforming at least one of the first mode signal and the second mode signal such that the first mode signal and the second mode signal are received by the combiner in a mutually incoherent state. A processing component for receiving and processing said combined signal is also comprised.

Abstract: An example embodiment may include a method for defining patterns for conductive paths in a dielectric layer. The method may include (a) forming a mask layer on the dielectric layer, (b) forming on the mask layer a set of longitudinally and parallel extending mask features, each mask feature including a mandrel having a pair of side wall spacers, the mask features being spaced apart such that gaps are formed between the mask features, (c) depositing an organic spin-on layer covering the set of mask features and filling the gaps, (d) etching a first trench in the organic spin-on layer, the first trench extending across at least a subset of the gaps and exposing the mask layer, and (e) depositing in a spin-on process a planarization layer covering the organic spin-on layer and filling the first trench.

Abstract: Methods and systems for analyzing design of an integrated circuit are described. An example method includes receiving a design layout for an integrated circuit and forming a plurality of images of portions of the design layout. The method also includes, for each image of a portion of the design layout, calculating a Fourier transform representation of the image and extracting values of pre-defined parameters from the Fourier transform representation. The method also includes comparing the extracted parameter values of the plurality of images to create a clustering model by unsupervised machine learning and to sort each image of a portion of the design layout into a cluster defined by the clustering model. The method also includes determining a number of images sorted into at least one cluster defined by the clustering model.

Abstract: The disclosed technology generally relates to magnetic devices, and more particularly to magnetic devices configured to generate a stream of domain walls propagating along an output magnetic bus. In an aspect, a magnetic device includes a magnetic propagation layer, which in turn includes a plurality of magnetic buses. The magnetic buses include at least a first magnetic bus, a second magnetic bus, and an output magnetic bus configured to guide propagating magnetic domain walls. The magnetic propagation layer further comprises a central region in which the magnetic buses converge and are joined together. In another aspect, a method includes providing the magnetic device and generating the stream of domain walls propagating along the output magnetic bus.

Abstract: The present disclosure relates to a memory hierarchy for a system-in-package. An example memory hierarchy is connectable to a processor via a memory management unit arranged for translating a virtual address sent by the processor into a physical address. The memory hierarchy has a data cache memory and a memory structure having at least a L1 memory array comprising at least one cluster. The memory structure comprises a first data access controller arranged for managing one or more banks of scratchpad memory of at least one of the clusters of at least the L1 memory array, comprising a data port for receiving at least one physical address and arranged for checking at run-time, for each received physical address, bits of the physical address to see if the physical address is present in the one or more banks of the at least one cluster of at least the L1 memory array.

Abstract: An image sensor comprises: an array (102) of pixels (104) arranged in rows and columns; readout circuitry (110) for reading out image information from pixels (104) in the array (102) of pixels (104); signal lines (112) for providing control signals to the pixels (104) in the array (102) and/or the readout circuitry (110); a programmable sequence controller (114) configured to control the control signals provided on the signal lines (112), said programmable sequence controller (114) comprising: at least one programmable signal controlling state machine (140), which is configured to define a sequence of states and to define control parameters for the states in the sequence, wherein the control parameters include the control signals to be provided on at least one signal line (112) for controlling at least one of a row of pixels (104) or the readout circuitry (110).

Abstract: A spectrometer is provided. The spectrometer may include an image sensor including a pixel array; and a photonics layer disposed on the pixel array and including a plurality of resonators and a plurality of couplers evanescently coupled to the plurality of resonators.

Abstract: The disclosure relates to a computer-implemented method for controlling on-demand service provisioning in a network, wherein the network comprises resources for providing a service. In the method, a service request is intercepted. At least one network function, indicated as a first network function, required for the service associated with the service request is determined. Then, the first network function is instantiated on a resource in the network for executing the service in the network.

Abstract: A multiplying digital-to-analog conversion circuit for use in an analog-to-digital converter is disclosed. In one aspect, the circuit comprises an input block including a capacitor and arranged for switchably connecting a first terminal of the capacitor to an input voltage signal during a first phase and to a fixed reference voltage during a second phase, a sub-analog-to-digital conversion circuit connected to a second terminal of the capacitor and arranged for quantizing a voltage on the capacitor during the second phase, a sub-digital-to-analog conversion circuit that receives the quantized version of the voltage and outputs an analog voltage derived from the quantized version, a feedback block including an amplifier connected to the second terminal of the capacitor and producing, at an amplifier output during a third phase, a residue signal corresponding to a combination of the input voltage signal and the analog voltage, and a feedback circuit.

Abstract: The disclosed technology generally relates to magnetic devices, and more particular to a magnetic structure, and a magnetic tunnel junction device and a magnetic random access memory including the magnetic structure. According to an aspect, a magnetic structure for a magnetic tunnel junction (MTJ) device includes a free layer, a tunnel barrier layer, a reference layer, a hard magnetic layer, and an inter-layer stack arranged between the hard magnetic layer and the reference layer. The inter-layer stack includes a first ferromagnetic sub-layer, a second ferromagnetic sub-layer and a non-magnetic spacer sub-layer. The non-magnetic spacer sub-layer is arranged in contact with and between the first ferromagnetic sub-layer and the second ferromagnetic sub-layer and is adapted to provide a ferromagnetic coupling of a magnetization of the first ferromagnetic sub-layer and a magnetization of the second ferromagnetic sub-layer.