Abstract: An LDMOS device in FinFET technology is disclosed. In one aspect, the device includes a first region substantially surrounded by a second region of different polarity. The device further includes a first fin in the first region, extending into the second region, the first fin including a doped source region connected with a first local interconnect. The device further includes a second fin in the second region, including a doped drain region connected with a second local interconnect. The device further includes a third fin parallel with the first and second fins including a doped drain region connected with the second local interconnect. The device further includes a gate over the first fin at the border between the first and second regions. A first current path runs over the first and second fins. A second current path runs over and perpendicular to the first fin towards the third fin.

Abstract: Example embodiments relate to active-passive waveguide photonic systems. An example embodiment includes a monolithic integrated active/passive waveguide photonic system. The system includes a substrate having positioned thereon at least one active waveguide and at least one passive waveguide. The at least one active waveguide and the at least one passive waveguide are monolithically integrated and are arranged for evanescent wave coupling between the waveguides. The at least one active waveguide and the at least one passive waveguide are positioned so that at least a portion of each waveguide does not overlap the other waveguide, both in a height direction and in a lateral direction with respect to the substrate.

Abstract: The disclosed technology generally relates to a switching device and more particularly to a switching device based on an active portion capable of switching from an insulating state to a conductive state. In an aspect, a switching device comprises an active portion interposed between two electrodes and capable of switching from an insulating state to a conducting state when a voltage higher than a threshold value is applied between the two electrodes. The threshold value is lowered by a dielectric permittivity distribution which produces a concentration of electrical field at a location within the active portion. Thus, the switching device may be devoid of a third control electrode.

Abstract: Embodiments described herein relate to a large area lens-free imaging device. One example is a lens-free device for imaging one or more objects. The lens-free device includes a light source positioned for illuminating at least one object. The lens-free device also includes a detector positioned for recording interference patterns of the illuminated at least one object. The light source includes a plurality of light emitters that are positioned and configured to create a controlled light wavefront for performing lens-free imaging.

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to transistors comprising germanium (Ge) in the channel, and to methods of manufacturing thereof. In one aspect, a field-effect transistor (FET) comprises an active region comprising germanium (Ge) and a gate stack formed on the active region. The gate stack comprises a Si-comprising passivation layer formed on the active region, an interfacial dielectric layer comprising SiOx (x>0) formed on the passivation layer, a dielectric capping layer comprising an interface dipole-forming material formed on the interfacial dielectric layer, a high-k dielectric layer formed on the dielectric capping layer and a gate electrode layer formed on the high-k dielectric layer.

Abstract: The disclosed technology generally relates to methods of fabricating a semiconductor device, and more particularly to methods of fabricating a ferroelectric field-effect transistor (FeFET). According to one aspect, a method of fabricating a FeFET includes forming a layer stack on a gate structure, wherein forming the layer stack comprises a ferroelectric layer followed by forming a sacrificial stressor layer. The method additionally includes heat-treating the layer stack to cause a phase transition in the ferroelectric layer. The method additionally includes, subsequent to the heat treatment, replacing the sacrificial stressor layer with a two-dimensional (2D) material channel layer. The method further includes forming a source contact and a drain contact contacting the 2D material channel layer.

Abstract: The disclosed technology generally relates to patterning structures in semiconductor fabrication, and more particularly to patterning structures using mask structures having bridged lines.

Abstract: The present disclosure relates to a method for cancelling spillover in a MIMO radar system. The method comprises (i) transmitting and receiving a signal in a transmit-receive pair, the received signal including a spillover signal; (ii) routing a part of the transmitted signal of the transmit-receive pair to the received signal to increase the power level of the spillover signal; and (iii) cancelling the spillover signal and the part of the transmitted signal by a spillover cancellation subsystem associated with the transmit-receive pair. Because the part of the transmitted signal corresponds to the spillover signal, both of these signals may be added together to result in a combined signal having a high enough power level to improve the functioning of the spillover cancellation subsystem.

Abstract: A variable delay circuit, which includes a digital-to-time converter (DTC) circuit and a controller, is disclosed. The DTC circuit includes a plurality of capacitors and a plurality of MOS switches that are turned on and off according to a control code. The DTC circuit receives an input pulse, applies a delay corresponding to the control code to the edge to be delayed, and outputs a delay pulse. The controller supplies a valid code indicating a delay amount as a control code during a period beginning from a predetermined time TCONST before the edge (positive edge) to be delayed of an input pulse REF up to the edge to be delayed. Further, the controller supplies, as the control code, a dummy code for turning on all of the plurality of MOS switches inside the DTC circuit immediately before the period.

Abstract: A method for an intermediary node to reduce a number of server-client sessions between a server (104) and a plurality of clients (102a, 102b, 102c) communicably connected to the server (104) over a network is disclosed. The intermediary node (106) intercepts a first request and a second request destined to the server (104) from a first client (102a; 102b; 102c) and a second client (102a; 102b; 102c). The intermediary node (106) establishes a server-client session, between the intermediary node (106) and the server (104), using the first request. If the first request overlaps in part with the second request and if a part of the second request is not overlapping with the first request, the intermediary node (106) updates the server-client session between the intermediary node (106) and the server (104) to include a part of the second request.

Abstract: A method and apparatus is disclosed for monitoring critical dimensions in a pattern of 1-dimensional and/or 2-dimensional features, produced on a substrate in a process step that is part of or related to a manufacturing process for producing a semiconductor device, the process step being performed in accordance with a predefined pattern design, wherein one or more metrology targets (1) are added to the pattern design. The targets comprise one or more versions of an asymmetric metrology mark, each version of the mark comprising a uniform portion (2) and a periodic portion (3), the latter comprising a regular array of parallel line-shaped features or an array of 2-dimensional features. The design width of the features is situated in a range situated around a nominal design width w0. A position-related parameter S is defined that is essentially proportional to the design widths in the range.

Abstract: The present disclosure relates to a device for measuring an optical absorption property of a fluid as function of wavelength. The device comprises a broadband light source for emitting light, a plurality of integrated optical waveguides for guiding this light, and a light coupler for coupling the emitted light into the integrated optical waveguides such that the light coupled into each integrated optical waveguide has substantially the same spectral distribution. The device also comprises a microfluidic channel for containing the fluid, arranged such as to allow an interaction of the light propagating through each waveguide with the fluid in the microfluidic channel. Each integrated optical waveguide comprises an optical resonator for filtering the light guided by the waveguide according to a predetermined spectral component. The spectral component corresponding to each waveguide is substantially different from the spectral component corresponding to another of the waveguides.

Abstract: The present disclosure provides a method for defining patterns for conductive paths in a dielectric layer. An example method includes forming a mask layer and forming a set of mandrels, each mandrel having a pair of side wall spacers. The method also includes etching the mask layer to form a first set of trenches in the mask layer. The method further includes covering the set of mandrels with a metal oxide planarization layer, the metal oxide planarization layer filling the first set of trenches. The method also includes etching back the metal oxide planarization layer. The method also includes removing the set of mandrels by etching, thereby forming trenches in the metal oxide planarization layer, the trenches extending between the pairs of side wall spacers. The method also includes etching the mask layer to form a second set of trenches in the mask layer.

Abstract: The present disclosure relates to reconfigurable voltaic modules. One example embodiment includes a photovoltaic module. The photovoltaic module includes a plurality of photovoltaic cells arranged in a grid having logical rows and columns. The photovoltaic module also includes a plurality of non-reconfigurable interconnects electrically interconnecting subsets of the plurality of photovoltaic cells to form a plurality of cell strings. In addition, the photovoltaic module includes a plurality of reconfigurable interconnects. Each cell string includes at least four photovoltaic cells connected in an electrical series from a first cell to a last cell, the first cell and the last cell being located on a same edge of the grid.

Abstract: Systems and methods providing a wakeup receiver for latency-critical applications are described herein. An example system includes a wakeup receiver communicatively coupled to a communication channel. The wakeup receiver is configured to monitor an input signal of the communication channel and down-convert the input signal to a DC signal. The system also includes an analog to digital converter (ADC) configured to digitize the DC signal and provide an ADC output. The system further includes a digital baseband (DBB) module configured to determine a received signal strength indication (RSSI) from the signal. The DBB is also configured to, for each packet, determine a respective packet length and compare the RSSI and respective packet length with a two-dimensional template. The DBB is additionally configured to, based on the comparison, determine an interrupt condition and, based on determining the interrupt condition, generate a wakeup signal.

Abstract: The disclosure relates to a method for forming a conformal coating on a substrate having a topography presenting a relief. One method of the disclosure includes setting the temperature of the substrate within the range 140-275° C., and coating an aqueous solution including a sol-gel precursor on said substrate. The disclosure also relates to a method for fabricating a battery, a capacitor, a catalyst, a photovoltaic cell or a sensor using such a method, and to an aqueous solution for use in such a method.

Abstract: In a first aspect, the present disclosure relates to a method for immobilizing a molecularly imprinted polymer onto a substrate, comprising providing a substrate having an amorphous carbon surface; and grafting the molecularly imprinted polymer onto the amorphous carbon surface.

Abstract: An integrated circuit (IC) chip having power and ground rails incorporated in the front end of line (FEOL) is disclosed. In one aspect, these power and ground rails are at the same level as the active devices and are therefore buried deep in the IC, as seen from the front of the chip. The connection from the buried interconnects to the source and drain areas is established by local interconnects. These local interconnects are not part of the back end of line, but they are for the most part embedded in a pre-metal dielectric layer onto which the BEOL is produced. In a further aspect, a power delivery network (PDN) of the IC is located in its entirety on the backside of the chip. The PDN is connected to the buried interconnects through suitable connections, for example metal-filled through-semiconductor vias or through silicon vias.

Abstract: A conformable matrix display device is provided with row conductors on the conformable carrier, each for a respective row of the matrix of pixel circuits. Each row conductor has serpentine trajectories in spaces between the pixel circuits in the respective row. Power supply voltage and selection pulse signals are transmitted over the same row conductors. Each row conductor is connected to supply voltage and selection inputs of the pixel circuits in the respective row. Each pixel circuit has a pulse transmission circuit coupled between the selection input and the control input of a de-multiplexing circuit for de-multiplexing data signals on column conductors. In this way the power supply voltage and the selection signal can be supplied making shared use of space between the pixel circuits. Thus the number of conductors in the matrix display device is reduced, which enables a greater distance between the conductors and/or bends in the conductors, which makes the circuit more stretchable and/or bendable.

Abstract: A solid state electrolyte and method of preparation is provided. The solid state electrolyte includes a plasticized polymer matrix with non-dissolved salt crystals embedded in the polymer matrix and wherein the non-dissolved crystals are suitable for dissolving ions in the plasticized polymer. The method of preparation includes dissolving a plasticizer and a polymer matrix in an organic solvent to obtain a plasticized polymer matrix; and mixing the salt crystals with the plasticized polymer matrix, wherein the weight ratio of salt crystals versus plasticizer and polymer matrix and organic solvent is above saturation concentration such that non-dissolved salt crystals are embedded in the plasticized polymer matrix.