Abstract: The disclosure relates to organic photovoltaic cells comprising a heterojunction structure formed by a first organic donor layer and a first organic acceptor layer, and further comprising a second organic acceptor layer adjacent to the first organic acceptor layer and/or a second organic donor layer adjacent to the first organic donor layer. The materials of the first acceptor layer and the second acceptor layer are selected to allow exciton dissociation by charge transfer at their interface, and to simultaneously allow exciton energy transfer at their interface. The materials of the first donor layer and the second donor layer are selected to allow exciton dissociation by charge transfer at their interface, and to simultaneously allow exciton energy transfer at their interface. Organic photovoltaic cells of the present invention may have a high short-circuit current density, a good open-circuit voltage and a good fill factor.

Abstract: A method of patterning organic semiconductor layers is disclosed. In one aspect, a method for forming a patterned organic semiconductor layer on a substrate includes providing a plurality of first electrodes on a substrate. The method additionally includes providing a patterned self-assembling monolayer at predetermined locations on each of the plurality of first electrodes. The method further includes providing a layer comprising an organic semiconductor material over the patterned self-assembling monolayer. A corresponding device and a photovoltaic module comprising such a device are also disclosed.

Abstract: A method of manufacturing a semiconductor device and the device resulted thereof is disclosed. In one aspect, the device has a heterogeneous layer stack of one or more III-V type materials, at least one transmission layer of the layer stack having a roughened or textured surface for enhancement of light transmission. The method includes (a) growing the transmission layer of a III-V type material, (b) providing a mask layer on the transmission layer, the mask layer leaving first portions of the transmission layer exposed, and (c) partially decomposing the first exposed portions of the transmission layer. Suitably redeposition occurs in a single step with decomposition, so as to obtain a textured surface based on crystal facets of a plurality of grown crystals. The resulting device has a light-emitting element. The transmission layer hereof is suitably present at the top side.

Abstract: The disclosed technology generally relates to semiconductor fabrication, and more particularly to a method of defining routing tracks for a standard cell semiconductor device, and to the standard cell semiconductor device fabricated using the method. In one aspect, a method of defining routing tracks in a target layer over a standard cell semiconductor device includes forming mandrels and forming a first set and a second set of spacers for defining the routing tracks. The standard cell semiconductor device includes a device layer and the routing tracks for contacting a device layer. The routing tracks include at least two pairs of off-center routing tracks, a central routing track arranged between the pairs of off-center routing tracks, and at least two edge tracks arranged on opposing sides of the at least two pairs of off-center routing tracks.

Abstract: A textile fabric containing a first electrically conductive thread and a second electrically conductive thread is disclosed. In one aspect, the first electrically conductive thread and the second electrically conductive thread cross at a first crossover point, wherein the textile fabric further contains an electrical connector establishing an electrical connection between the first electrically conductive thread and the second electrically conductive thread. The electrical connector contains a first contact pad in electrical contact with the first electrically conductive thread, a second contact pad in electrical contact with the second electrically conductive thread, and a first stretchable electrical interconnection connecting the first contact pad with the second contact pad. The first contact pad and the second contact pad are provided at a location different from the location of the first crossover point.

Abstract: An example embodiment relates to a photonic integrated circuit device and a method for its manufacture. An example device includes a planar detector having at least one photodetector. The device may further include a waveguide layer arranged substantially parallel to the planar detector, the waveguide layer including a first integrated waveguide for guiding a first light signal. A cavity may be formed in the waveguide layer in a region spaced away from the edges of the waveguide layer such as to terminate the first integrated waveguide in that region. A first reflective surface may be provided in the cavity to reflect the first light signal guided by the first integrated waveguide toward a first photodetector of the planar detector.

Abstract: A hardware implementation of a temporal memory system is disclosed. One aspect includes at least one array of memory cells logically organized in rows and columns, wherein each of the memory cells is adapted for storing a scalar value and adapted for changing the stored scalar value. The hardware implementation additionally includes an input system adapted for receiving an input frame as input and for creating a representation for the input, where the input comprises information for addressing the memory cells in the at least one array. The hardware implantation additionally includes at least one addressing unit for identifying a memory cell in the at least one array with a row address and a column address.

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to transistor devices such as metal-oxide-semiconductor (MOS) transistor devices. In one aspect, a transistor device comprises a channel region in a substrate partially delimited by a source and a drain junction at a main surface of the substrate. A first dielectric layer stack is arranged on the channel region, such that an orthogonal projection of the first dielectric layer stack on the main surface defining a first area is between and does not overlap the junctions and. A second dielectric layer stack is formed laterally adjacent to and in contact with the first dielectric layer stack, such that an orthogonal projection of the second dielectric layer stack overlaps the junction and defines a second area. A metal gate layer is formed on the first and second dielectric layer stacks, where an orthogonal projection of the metal gate layer on the main surface overlaps the first area and the second area.

Abstract: A method of provisioning a service in a communication network is described, in which the service comprises at least one virtual network function and at least one virtual network path, which at least one virtual network function and at least one virtual network path are to be implemented in the communication network. The method including obtaining affinity constraints and/or anti-affinity constraints relating to mapping the at least one virtual network path onto the communication network, optionally obtaining affinity constraints and/or anti-affinity constraints relating to mapping the at least one virtual network function onto the communication network, and mapping the at least one virtual network function and at least one virtual network path onto the communication network subject to said constraints.

Abstract: The disclosed technology generally relates to computation devices, and more particularly to majority gate devices configured for computation based on spin waves. In one aspect, a majority gate device comprises cells that are configurable as spin wave generators or spin wave detectors. The majority gate device comprises an odd number of spin wave generators, and at least one spin wave detector. The majority gate device additionally comprises a waveguide adapted for guiding spin waves generated by the spin wave generators. The spin wave generators and the at least one spin wave detector are positioned in an inline configuration along the waveguide such that, in operation, interference of the spin waves generated by the spin wave generators can be detected by the at least one spin wave detector. The interference of the spin waves corresponds to a majority operation of the spin waves generated by the spin wave generators.

Abstract: Embodiments described herein include an antimicrobial substrate surface. An example embodiment includes a structure that includes an antimicrobial surface on a substrate. The antimicrobial surface includes a plurality of nanostructures. Each nanostructure includes a nanopillar on the substrate. The nanopillar has a height. Each nanostructure also includes a head covering a distal end and at least part of the height of the nanopillar.

Abstract: The present disclosure relates to a fluid analysis device which comprises a sensing device for analyzing a fluid sample, the sensing device comprising a micro-fluidic component for propagating the fluid sample and a microchip configured for sensing the fluid sample in the micro-fluidic component; a sealed fluid compartment containing a further fluid, the compartment being fluid-tight connected to the sensing device and adapted for providing the further fluid to the micro-fluidic component when the sealed fluid compartment is opened; and an inlet for providing the fluid sample to the micro-fluidic component. Further, the present disclosure relates to a method for sensing a fluid sample using the fluid analysis device.

Abstract: A semiconductor device for electric discharge protection is disclosed. In one aspect, the semiconductor device includes a substrate having a p-type doping. The semiconductor device includes a first well and a second well having an n-type doping and arranged spaced apart within a surface layer of the substrate, and a third well having a p-type doping and arranged in the surface layer of the substrate between the first well and the second well. The semiconductor device further includes an emitter region and a base contact region having a p-type doping and arranged within a surface layer of the first well, and a collector region having a p-type doping. The collector region is arranged at least partly within a surface layer of the third well and such that it overlaps both of the first well and the second well. An integrated circuit including a semiconductor device is also provided.

Abstract: The disclosure relates to systems and methods for acquisition of biosignals with motion sensor-based artifact compensation. One example embodiment is a system for acquisition of biosignals from a subject. The system includes at least one biosensor worn over a first location of a body part of the subject configured for biosignal measurement and providing a measured biosignal. The system also includes a plurality of inertial motion sensors worn over a plurality of locations of the body part of the subject. Each of the inertial motion sensors is configured for providing a motion vector signal. The system further includes a biosignal adaptation unit configured for receiving and adapting the measured biosignal. In addition, the system includes a motion estimation unit. Further, the system includes a digital filter unit. At least one of the plurality of inertial motion sensors is mechanically connected to the at least one biosensor.

Abstract: The present disclosure relates to a method for bonding semiconductor components. A semiconductor component comprising microbumps on a planar bonding surface is prepared for bonding by applying a photosensitive polymer layer on the bonding surface. The average thickness of the initial polymer layer in between the microbumps is similar to the average height of the microbumps. In a lithography process, the polymer is removed from the upper surface of the microbumps and from areas around the microbumps. The polymer is heated to a temperature at which the polymer flows, resulting in a polymer layer that closely adjoins the microbumps, without exceeding the microbump height. The closely adjoining polymer layer may have a degree of planarity substantially similar to a planarized layer.

Abstract: The disclosed technology relates generally to semiconductor devices and more particularly to three dimensional semiconductor memory devices, such as vertical three dimensional non-volatile memory devices. In one aspect, a method of fabricating a memory device comprises providing, on a substrate, an alternating stack of control gate layers and dielectric layers. The method additionally includes forming a memory block. comprising forming at least one memory hole through the alternating stack, where the at least one memory hole comprises on its sidewalls a stack of a programmable material, a channel material and a dielectric material, thereby forming at least one memory cell. The method additionally comprises removing a portion of the alternating stack to form at least one trench, where the at least one trench forms at least part of a boundary of the memory block.

Abstract: According to an aspect of the present inventive concept there is provided a system comprising: a conductive textile including conductive fibers, an electronic circuit unit arranged on a first main surface of the conductive textile and including circuitry and a carrier supporting the circuitry, the carrier having a first main surface and a second main surface facing the first main surface of the textile and including a through-hole extending from the first main surface to the second main surface, a conductive pin including an leg segment arranged at least partly in the through-hole, and a grip segment arranged to grip about at least one fiber of the conductive textile. There is also provided a method for mounting an electronic circuit unit on a conductive textile.

Abstract: A sequential integration process is described. An example process involves forming a wafer stack by bonding a first wafer to a second wafer with a front side of the first wafer facing a front side of the second wafer, the first wafer including a first device region formed on the front side of the first wafer and including a set of semiconductor devices. The example process involves, subsequent to forming the wafer stack, forming a second device region on a back side of the first wafer, the second device region including a set of semiconductor devices. The example process involves forming at least one interconnection layer on the second device region for electrically interconnecting the semiconductor devices of the second device region. The example process also involves forming at least one via extending through the wafer stack from the at least one interconnection layer and through the first wafer.

Abstract: LED chip packaging assembly that facilitates an integrated method for mounting LED chips as a group to be pre-wired to be electrically connected to each other through a pattern of extendable metal wiring lines is provided. LED chips which are electrically connected to each other through extendable metal wiring lines, replace pick and place mounting and the wire bonding processes of the LED chips, respectively. Wafer level MEMS technology is utilized to form parallel wiring lines suspended and connected to various contact pads. Bonding wires connecting the LED chips are made into horizontally arranged extendable metal wiring lines which can be in a spring shape, and allowing for expanding and contracting of the distance between the connected LED chips. A tape is further provided to be bonded to the LED chips, and extended in size to enlarge distance between the LED chips to exceed the one or more prearranged distances.

Abstract: The disclosed technology relates to a memory device for a dynamic random access memory, or DRAM. In one aspect, the memory device includes a substrate supporting a semiconductor device layer in which a plurality of semiconductor devices are formed. The memory device may further include an interconnection portion formed above the substrate and including a number of metallization levels and dielectric layers, the interconnection portion being adapted to interconnect said semiconductor devices. The memory device may further include a plurality of bit cell stacks arranged in the interconnection portion, each bit cell stack including a plurality of bit cells. Further, such bit cells may include elements such as a charge storage element, a write transistor, and a read transistor.