Abstract: A method for removing a hardened photoresist from a semiconductor substrate. An example method for removing a hardened photoresist layer from a substrate comprising a low-? dielectric material preserving the characteristics of the low-?dielectric material includes: a)—providing a substrate comprising a hardened photoresist layer and a low-? dielectric material at least partially exposed; b)—forming C?C double bonds in the hardened photoresist by exposing the hardened photoresist to UV radiation having a wavelength between 200 nm and 300 nm in vacuum or in an inert atmosphere; c)—breaking the C?C double bonds formed in step b) by reacting the hardened photoresist with ozone (O3) or a mixture of ozone (O3) and oxygen (O2) thereby fragmenting the hardened photoresist; and d)—removing the fragmented photoresist obtained in step c) by wet processing with cleaning chemistries.

Abstract: A digital receiver is disclosed. In one aspect, the receiver includes a receiving module for receiving packetized data. The receive may further include a first processing module for packet detection having a first programmable processor. The receiver may further include a second processing module for demodulation and packet decoding having a second programmable processor. The receiver may further include a first digital receive controller having a third processor arranged for being notified of detection of data by the first processing module and for activating the second processing module.

Abstract: A circuit for adaptive feedback equalization is disclosed. In one aspect, the circuit includes a frequency-domain feedforward filtering section and a feedback filtering section, a slicer to slice a block of equalized symbols, a summing module for summing outputs of the filtering sections thereby yielding the block of equalized symbols. First and second updating modules provide coefficient updates to the filtering sections. The updating modules are fed with a frequency-domain converted block of error signals indicating the difference between the block of equalized symbols at the slicer input and the block of sliced symbols at the slicer output and for computing updates using the frequency-domain converted block of error signals. A time-domain compensation module receives a time-domain version of the updated filter coefficients of the feedback filtering section and symbols of the block of sliced symbols. It adds a feedback error compensation signal to the block of equalized symbols.

Abstract: Methods and apparatuses for cleaning a surface of a substrate are presented. The method comprises positioning a substrate at a controllable distance from a piezoelectric transducer, supplying a cleaning liquid between the substrate and the transducer, applying an oscillating acoustic force to the cleaning liquid by actuating the transducer, and moving the transducer relative to the substrate. The method further comprises, while moving the transducer relative to the substrate, measuring a value that indicates a distance between a surface of the substrate and the transducer, comparing the measured value to a desired value, and adjusting the distance between the surface and the transducer so that the measured value is maintained substantially equal to the desired value. The measured value may be the distance between the surface of the substrate and the transducer or a phase shift between an alternating current and voltage applied to the transducer.

Abstract: Disclosed are thermoelectric systems and methods for manufacturing thermoelectric systems. In one embodiment, a thermoelectric system include a flexible structure and at least one thermocouple unit integrated in or attached to the flexible structure, where each thermocouple unit comprises at least one thermocouple and at least one flexible radiator element thermally connected to a first end of the at least one thermocouple. In another embodiment, a method includes providing a flexible structure, forming at least one thermocouple unit comprising at least one thermocouple and at least one flexible radiator element thermally connected to a first end of the at least one thermocouple, and integrating the at least one thermocouple unit in or attaching the at least one thermocouple unit to the flexible structure.

Abstract: Resistive memory elements and arrays of resistive memory elements are disclosed. In one embodiment, a resistive memory element includes a top electrode element lying in a plane parallel to a reference plane, and having, in perpendicular projection on the reference plane, a top electrode projection; a bottom electrode element lying in a plane parallel to the reference plane, and having, in perpendicular projection on the reference plane, a bottom electrode projection; and an active layer with changeable resistivity interposed between the top electrode element and the bottom electrode element. The top electrode projection and the bottom electrode projection overlap in an overlapping region that comprises a corner of the top electrode projection and/or a corner of the bottom electrode projection, and an area of the overlapping region constitutes less than 10% of a total projected area of the top electrode element and the bottom electrode element on the reference plane.

Abstract: Method for manufacturing a non-volatile memory comprising at least one array of memory cells on a substrate of a semiconductor material, the memory cells being self-aligned to and separated from each other by STI structures, the memory cells comprising a floating gate having an inverted-T shape in a cross section along the array of memory cells, wherein the inverted T shape is formed by oxidizing an upper part of the sidewalls of the floating gates thereby forming sacrificial oxide, and subsequently removing the sacrificial oxide simultaneously with further etching back the STI structures.

Abstract: Disclosed are methods for manufacturing a floating gate memory device and the floating gate memory device thus obtained. In one embodiment, a method is disclosed that includes providing a semiconductor-on-insulator substrate, forming at least two trenches in the semiconductor-on-insulator substrate, and, as a result of forming the at least two trenches, forming at least one elevated structure. The method further includes forming isolation regions at a bottom of the at least two trenches by partially filling the at least two trenches, thermally oxidizing sidewall surfaces of at least a top portion of the at least one elevated structure, thereby providing a gate dielectric layer on at least the exposed sidewall surfaces; and forming a conductive layer over the at least one elevated structure, the gate dielectric layer, and the isolation regions to form at least one floating gate semiconductor memory device.

Abstract: A method and system for converting application code into optimized application code or into execution code suitable for execution on a computation engine with an architecture comprising at least a first and a second level of data memory units are disclosed. In one aspect, the method comprises obtaining application code, the application code comprising data transfer operations between the levels of memory units. The method further comprises converting at least a part of the application code. The converting of application code comprises scheduling of data transfer operations from a first level of memory units to a second level of memory units such that accesses of data accessed multiple times are brought closer together in time than in the original code.

Abstract: A signal processing device is adapted for simultaneous processing of at least two process threads in a multi-processing manner. The device comprises a plurality of functional units capable of executing word- or subword-level operations on data. The device further comprises means for interconnecting the plurality of functional units, the means for interconnecting supporting a plurality of dynamically switchable interconnect arrangements, and at least one of the interconnect arrangements interconnects the plurality of functional units into at least two non-overlapping processing units each with a pre-determined topology. The device further comprises at least two control modules each assigned to one of the processing units.

Abstract: A metal nanoantenna for use in a biosensing device is disclosed. The metal nanoantenna is arranged to exhibit at least two particle plasmon resonances or surface plasmon resonances (SPRs). The nanoantenna is for use in a sensor and allows detection at low concentration of biological components. In one aspect, the nanoantenna can have an asymmetric structural configuration and spectrally separated resonances. In one aspect, there is a location in its structure providing local electromagnetic field enhancement at all of the SPRs. The metal nanoantenna can be used for background free measuring of a quantity of a biological component.

Abstract: The present disclosure is related to method for producing a semiconductor device comprising the steps of: providing a semiconductor substrate (1), comprising active components on the surface of said substrate, depositing a top layer (2) of dielectric material on the surface of said substrate or on other dielectric layers present on said surface, etching at least one first opening (7) at least through said top layer, filling said opening(s) at least with a first conductive material (8), and performing a first CMP step, to form said first conductive structures (3,26), etching at least one second opening (13) at least through said top layer, filling said opening(s) at least with a second conductive material (10), and performing a second CMP step, to form said second conductive structures (4,24), wherein the method comprises the step of depositing a common CMP stopping layer (5,25) on said dielectric top layer, before the steps of etching and filling said first opening(s), so that said same CMP stopping layer is

Abstract: The present invention relates to a method for fabricating an organic device, said method comprising: (i) Providing a substrate (1) having a surface comprising electrical contact structures (4) and a dielectric portion (3), (ii) Providing a first temporary protection layer (9) on some or all of said electrical contact structures (4), (iii) Providing a first surface modification layer (6) on the dielectric portion (3) and/or providing a third surface modification layer (10) on said electrical contact structures (4) not protected in step (ii), (iv) Removing the first temporary protection layer (9), (v) Providing a second surface modification layer (5) on the electrical contact structures that where protected in step (ii), and (vi) Providing said first surface modification layer (6) on the dielectric portion (3), if it was not provided in step (iii), and (vii) Providing an organic semiconductor layer (7) on top of at least part of said first surface modification layer (6) and on top of said second (5) surface mod

Abstract: An organic photo-detecting field-effect device is presented, the device comprising a first layer comprising an organic semi-conducting material, the first layer acting as an accumulation layer and as a charge transport layer for a first type of charge carriers, and a second layer comprising a second material, the second layer acting as a an accumulation layer for a second type of charge carriers. Charges collected in the second layer influence the charge transport in the first layer. The second material may be an organic semi-conducting material or a metal. At the interface between the first layer and the second layer a heterojunction is formed in the case of an organic semi-conducting second material, and a Schottky barrier is formed in the case of a metal second material, giving rise to an efficient exciton splitting. Different geometries and operation modes facilitating the removal of the collected photo-generated charge carriers during the reset period of the device are presented.

Abstract: A method for making a solution for forming a titanium oxide sol-gel layer. Is provided. The method comprises the steps of: mixing an acid with water thereby obtaining a first mixture, mixing the first mixture with a water miscible alcohol, thereby obtaining a second mixture, mixing an amine compound, e.g., ethanolamine, to the second mixture, thereby obtaining a third mixture, waiting enough time for the third mixture to reach room temperature, e.g. from 10 to 15 minutes, and adding a titanium oxide precursor to the third mixture, thereby obtaining the solution.

Abstract: A method is disclosed for packaging a device, e.g., for bio-medical applications. In one aspect, the method includes obtaining a component on a substrate and separating the component and a first part of the substrate from a second part of the substrate using at least one physical process inducing at least one sloped side wall on the first part of the substrate. The method also includes providing an encapsulation for the chip. The resulting packaged chip advantageously has a good step coverage resulting in a good hermeticity, less sharp edges resulting in a reduced risk of damaging or infection after implantation and has a relatively small packaged volume compared to conventional big box packaging techniques.

Abstract: A method for adding fine grain tuning circuitry to an integrated circuit design is disclosed. In one aspect, the method includes providing a design elaborated to have representations of generic logic components and interconnections between the generic logic components, automatically selecting those of the generic logic components which are in critical timing paths, and amending the design to add the fine grain tuning circuitry automatically to the selected generic logic components in the elaborated design for use in maintaining the critical timing paths during operation of the integrated circuit. By adding the circuitry at this lower level of design while it is still generic, before the synthesis stage, the additions can be made more quickly and with less disruption to the design process.

Abstract: A sensor is disclosed. In one aspect, the sensor includes at least one resistive switching sensing element which has a resistive switching layer that can be switched from a high resistance state to a low resistance state by creating a first electric field over the resistive switching layer and that can be switched from the low resistance state to the high resistance state by creating a second electric field over the resistive switching layer.

Abstract: Embodiments of the present disclosure provide a method to fabricate a hetero-junction in a Tunnel Field Effect Transistor (TFET) device configuration (e.g. in a segmented nanowire TFET). Since in prior art devices the highly doped source is in direct contact with the lowly doped or undoped channel, some amount of dopants will diffuse from the source to the channel which cannot be avoided due to the source deposition thermal budget. This out-diffusion reduces the steepness of the doping profile and hence deteriorates the device operation. Particular embodiments comprise the insertion of a thin transition layer in between the source region and channel region such that the out-diffusion is within a very limited region of a few nm, guaranteeing extremely good doping abruptness thanks to the lower diffusion of the dopants in the transition layer. The transition layer avoids the direct contact between the highly doped (e.g. Ge or SiGe) source region and the lowly doped or undoped (e.g.

Abstract: A method for fabricating a crystalline silicon photovoltaic cell is disclosed. In one aspect, the method includes a) providing a crystalline silicon substrate of a first dopant type, b) performing an implantation, thereby introducing dopants of a second type opposite to the first type at a front side of the crystalline silicon substrate, c) after the implantation, depositing a hydrogen containing layer on the front surface of the substrate, and d) after depositing the hydrogen containing layer, performing a thermal treatment, thereby electrically activating the dopant of the second type.