Abstract: A microfluidic device is described. The microfluidic device comprises at least one transport channel and at least one working chamber, wherein the at least one transport channel and the at least one working chamber are separated from each other by a common deformable wall. The at least one transport channel is for containing a transport fluid and the at least one working chamber is for containing a working fluid. The microfluidic device comprises at least one pair of electrodes for changing the pressure on the working fluid such that when the pressure on the working fluid is changed, the deformable wall deforms, resulting in a change of the cross-section of the at least one transport channel. The working chamber comprises a flexible wall different from the common deformable wall and at least one electrode of the at least one pair of electrodes is provided on the flexible wall.

Abstract: The present disclosure relates to a system comprising at least a first and a second essentially analogue portion and an essentially digital portion, the analogue portions forming a part of a unidirectional circular network. First communication means is provided between the digital portion and the first analogue portion. Second communication means is provided between the first and second analogue portions. The first and second communication means are configurable for establishing communication between the digital portion and the second analogue portion. The first and second communication means are arranged to determine if a packet communicated over the first or second communication means is of interest for any of the analogue portions.

Abstract: The present invention is related to the field of semiconductor processing and, more particularly, to the formation of low resistance layers on germanium substrates. One aspect of the present invention is a method comprising: providing a substrate on which at least one area of a germanium layer is exposed; depositing over the substrate and said germanium area a metal, e.g., Co or Ni; forming over said metal, a capping layer consisting of a silicon oxide containing layer, of a silicon nitride layer, or of a tungsten layer, preferably of a SiO2 layer; then annealing for metal-germanide formation; then removing selectively said capping layer and any unreacted metal, wherein the temperature used for forming said capping layer formation is lower than the annealing temperature.

Abstract: A substrate is described that is suitable for surface enhanced optical detection. The substrate comprises an electrically conductive layer (110), such as for example a gold layer. It furthermore comprises at least one nanoparticle (1404) comprising an electrically conductive portion. The electrically conductive portion in some embodiments provides an opening to an underlying material. Such at least one nanoparticles (1404) thus may for example be a nanoring, a nanodisc, or a non-spherical nanoshell. The substrate furthermore comprises a dielectric spacer (1406) for spacing the electrically conductive layer from the at least one nanoparticles. The dielectric spacer (1406) is a dielectric material substantially only present under the at least one nanoparticle (1404), leaving the electrically conductive layer (110) uncovered from dielectric material at positions away from the nanoparticles (1404).

Abstract: A test circuit and method for testing through-silicon-vias (TSVs) in three-dimensional integrated circuits (ICs) during each phase of manufacturing is disclosed. In one aspect, the method includes testing for faults in each individual TSV, TSV-under-test, shorts between a TSV-under-test, and TSVs in close proximity and for connections between the TSV-under-test and another tier in the ICs. A test circuit has three switchable current paths connected to a power supply via a pull-up resistor and switches: a calibration path, a short path, and a current measurement path. A power supply is connected to the measurement path, and the calibration path and the short path are connected to ground via respective pull-down resistors. For each TSV-under-test, the desired operation mode is selected by the closure of different combinations of switches. The current flowing through the pull-up resistor in each operation mode indicates whether the TSV-under-test has passed or failed the test.

Abstract: A semiconductor device and a method of manufacturing the device is disclosed. In one aspect, a method includes providing a substrate, providing a first epitaxial semiconducting layer on top of the substrate, and forming a one- or two-dimensional repetitive pattern, each part of the pattern having an aspect ratio in the range of about 0.1 to 50.

Abstract: A radio frequency modulator is disclosed that includes a finite impulse response filter including a first modulator element having a first gain and configured to receive a first input signal and produce a first output signal, a second modulator element having a second gain and configured to receive a second input signal delayed with respect to the first input signal and produce a second output signal, a third modulator element having a third gain and configured to receive a third input signal delayed with respect to the second input signal and produce a third output signal, and a fourth modulator element having a fourth gain and configured to receive a fourth input signal delayed with respect to the third input signal and produce a fourth output signal. The first, second, third, and fourth gains are each different and are based on coefficients of the finite impulse response filter.

Abstract: Ni3Si2 FUSI gates can be formed inter alia by further reaction of NiSi/Ni2Si gate stacks. Ni3Si2 behaves similarly to NiSi in terms of work function values, and of modulation with dopants on SiO2, in contrast to Ni-rich silicides which have significantly higher work function values on HfSixOy and negligible work function shifts with dopants on SiO2. Formation of Ni3Si2 can applied for applications targeting NiSi FUSI gates, thereby expanding the process window without changing the electrical properties of the FUSI gate.

Abstract: A III-nitride device is provided comprising a semiconductor substrate; a stack of active layers on the substrate, each layer comprising a III-nitride material; a gate, a source and a drain contact on the stack, wherein a gate, a source and a drain region of the substrate are projections of respectively the gate, the source and the drain contact in the substrate; and a trench in the substrate extending from a backside of the substrate (side opposite to the one in contact with the stack of active layers) to an underlayer of the stack of active layers in contact with the substrate, the trench completely surrounding the drain region, being positioned in between an edge of the gate region towards the drain and an edge of the drain region towards the gate and having a width such that the drain region of the substrate is substantially made of the semiconductor material.

Abstract: An integrated circuit for an imaging system is disclosed. In one aspect, an integrated circuit has an array of optical sensors, an array of optical filters integrated with the sensors and configured to pass a band of wavelengths onto one or more of the sensors, and read out circuitry to read out pixel values from the sensors to represent an image. Different ones of the optical filters are configured to have a different thickness, to pass different bands of wavelengths by means of interference, and to allow detection of a spectrum of wavelengths. The read out circuitry can enable multiple pixels under one optical filter to be read out in parallel. The thicknesses may vary non monotonically across the array. The read out, or later image processing, may involve selection or interpolation between wavelengths, to carry out spectral sampling or shifting, to compensate for thickness errors.

Abstract: The present disclosure is related to a method for forming a catalyst nanoparticle on a metal surface, the nanoparticle being suitable for growing a single nanostructure, in particular a carbon nanotube, the method comprising at least the steps of: providing a substrate, having a metal layer on at least a portion of the substrate surface, depositing a sacrificial layer at least on the metal layer, producing a small hole in the sacrificial layer, thereby exposing the metal layer, providing a single catalyst nanoparticle into the hole, removing the sacrificial layer. The disclosure is further related to growing a carbon nanotube from the catalyst nanoparticle.

Abstract: Calibration method for calibrating transient behavior of a TLP test system. The system comprises a TLP generator, probe needles, nominally impedance matched transmission lines and measurement equipment, connected between the transmission lines and the TLP generator, for detecting transient behavior of a device under test by simultaneously capturing voltage and current waveforms as a result of generated pulses. The calibration method comprises (a) applying the TLP test system on an open and capturing first voltage and current waveforms; (b) applying the TLP test system on a calibration element having a known finite impedance and a known transient response and capturing second voltage and current waveforms; (c) transforming the captured first and second current and voltage waveforms to the frequency domain, and (d) determining calibration data for the transient behavior of the TLP test system on the basis of the transformed first and second voltage and current waveforms.

Abstract: A method for manufacturing a III-nitride HEMT having a gate electrode and source and drain ohmic contacts is provided, comprising providing a substrate; forming a stack of III-nitride layers on the substrate; forming a first passivation layer comprising silicon nitride overlying and in contact with an upper layer of the stack of III-nitride layers, wherein the first passivation layer is deposited in-situ with the stack of III-nitride layers; forming a dielectric layer overlying and in contact with the first passivation layer; forming a second passivation layer comprising silicon nitride overlying and in contact with the dielectric layer wherein the second passivation layer is deposited at a temperature higher than 450° C. by LPCVD or MOCVD or any equivalent technique; and thereafter forming the source and drain ohmic contacts and the gate electrode.

Abstract: A method is presented for obtaining characteristics of a target physical entity by providing an excitation signal to the target physical entity and simultaneously measuring the response of the target physical entity. Analog signal processing is performed on the measured response to eliminate artifacts arising from a signal path outside the target physical entity and determining the characteristics from the signal processed measured response. The excitation signal and the analog signal processing are selected such that after analog signal processing of the measured signal, the analog measured signal contains artifacts which are localized in time.

Abstract: A method for detecting embedded voids present in a structure formed in or on a semiconductor substrate is described. The method includes performing a processing step P1 for forming the structure; measuring the mass M1 of the substrate; performing thermal treatment; measuring the mass M2 of the substrate; calculating the mass difference between the mass of the substrate measured before and after the performed thermal treatment; and deducing the presence of embedded voids in the structure by comparing the mass difference with a pre-determined value.

Abstract: The present preferred embodiments relate to a method for the synthesis of a compound having the following general formula: the method comprising the step of reacting, in presence of a diprotic acid having a negative pKa, a compound having the general formula: wherein R1 and R2 are organic groups and wherein X and Y are independently selected from the group consisting of hydrogen, chloro, bromo, iodo, boronic acid, boronate esters, borane, pseudohalogen and organotin. It further relates to compounds so obtained and to compounds resulting from the ring closure of compound (II).

Abstract: A method of forming a surface passivation layer on a surface of a crystalline silicon substrate is disclosed. In one aspect, the method includes depositing an Al2O3 layer on the surface, the Al2O3 layer having a thickness not exceeding about 15 nm; performing an outgassing process at a temperature in the range between about 500° C. and 900° C., after the deposition of the Al2O3 layer on the surface; and after the outgassing process, depositing at least one additional dielectric layer such as a silicon nitride layer and/or a silicon oxide layer on the Al2O3 layer.

Abstract: A system is disclosed that includes an oven and a micromechanical oscillator inside the oven configured to oscillate at a predetermined frequency at a predetermined temperature, where the predetermined frequency is based on a temperature dependency and at least one predetermined property. The system further includes an excitation mechanism configured to excite the micromechanical oscillator to oscillate at the predetermined frequency and a temperature control loop configured to detect a temperature of the micromechanical oscillator using resistive sensing, determine whether the temperature of the micromechanical oscillator is within a predetermined range of the predetermined temperature based on the temperature dependency and the at least one predetermined property in order to minimize frequency drift, and adapt the temperature of the micromechanical oscillator to remain within the predetermined range.

Abstract: A substrate treating method comprising a step of preparing a semiconductor substrate (W, 11) which has an oxide film (13, 14) containing at least one of a rare earth oxide and an alkaline earth oxide, at least a portion of the oxide film (13, 14) being exposed, and a rinse step of supplying the oxide film (13, 14) on the semiconductor substrate (W, 11) with a rinse liquid made of an alkaline chemical or an organic solvent. Preferably, the alkaline chemical is an alkaline aqueous solution having a pH of more than 7. Further, preferably, the organic solvent is a high concentration organic solvent having a concentration of substantially 100%.

Abstract: A method to fabricate a hetero-junction in a Tunnel Field Effect Transistor device configuration (e.g. in a segmented nanowire TFET) is provided. A thin transition layer is inserted in between the source region and channel region such that the out-diffusion is within a very limited region of a few nm, guaranteeing extremely good doping abruptness thanks to the lower diffusion of the dopants in the transition layer. The transition layer avoids the direct contact between the highly doped source region and the lowly doped or undoped channel and allows to contain the whole doping entirely within the source region and transition layer. The thickness of the transition layer can be engineered such that the transition layer coincides with the steep transition step from the highly doped source region to the intrinsic region (channel), and hence maximizing the tunneling current.