Abstract: A method for fabricating a photovoltaic module is disclosed. In one aspect, the method includes: providing a plurality of photovoltaic substrates having a front side; attaching the plurality of photovoltaic substrates to a transparent carrier with the front side of the photovoltaic substrates facing the carrier; and rear side processing of the plurality of photovoltaic substrates for forming photovoltaic cells, wherein rear side processing includes a single metallization process for forming electrical contacts to n-type regions and to p-type regions at the rear side of the plurality of photovoltaic cells and for interconnecting the photovoltaic cells within the photovoltaic module.

Abstract: A tunnel field effect transistor (TFET) and method of making the same is provided. The TFET comprises a source-channel-drain structure and a gat electrode. The source region comprises a first source sub-region which is doped with a first doping profile with a dopant element of a first doping type having a first peak concentration and a second source sub-region close to a source-channel interface which is doped with a second doping profile with a second dopant element with the same doping type as the first dopant element and having a second peak concentration. The second peak concentration of the second doping profile is substantially higher than the maximum doping level of the first doping profile close to an interface between the first and the second source sub-regions.

Abstract: A new, effective and cost-efficient method of introducing Fluorine into Hf-based dielectric gate stacks of planar or multi-gate devices (MuGFET), resulting in a significant improvement in both Negative and Positive Bias Temperature Instabilities (NBTI and PBTI) is provided. The new method uses an SF6 based metal gate etch chemistry for the introduction of Fluorine, which after a thermal budget within the standard process flow, results in excellent F passivation of the interfaces. A key advantage of the method is that it uses the metal gate etch for F introduction, requiring no extra implantations or treatments. In addition to the significant BTI improvement with the novel method, a better Vth control and increased drive current on MuGFET devices is achieved.

Abstract: A method for single side texturing of a crystalline semiconductor substrate (10) comprises: providing a substrate (10), for example a semiconductor substrate, comprising a first surface (12) and a second surface (14) opposite to one another with respect to the substrate (10); providing a masking layer (21) with a random pattern on the first surface (12) of the substrate (10); and etching the substrate (10) in a polishing solution, thereby texturing the first surface (12) of the substrate (10) and polishing the second surface (14) in a single wet etching step.

Abstract: The present disclosure is related to a method for sharpening the tip of a microprobe, in particular a neural probe or an array of neuroprobes having a common base portion. The probes have a constant thickness and a chisel-shaped tip portion. The probes are attached to the slanted side of a wedge-shaped carrier, with the probe tips placed in close proximity to the edge of the carrier, for example extending over said edge. The base of the carrier is then subjected to a grinding step, possibly followed by a polishing step, so that the probe tips of the probes are ground to form a sharp pointed tip shape.

Abstract: A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function.

Abstract: A circuit and method for providing a digital output indicative of the time at which an event occurred is disclosed. In one aspect, the circuit includes a fine timing circuit configured to determine in which sub-interval of a clock period the event occurred, and a correction circuit configured to correct an erroneous offset between a first and second clock signals in the fine timing circuit. The correction circuit includes a synch circuit configured to determine in which half of the clock period the event occurred so as to correct for erroneous offset in the fine timing circuit.

Abstract: The present invention is related to a method for manufacturing a low defect interface between a dielectric material and an III-V compound. More specifically, the present invention relates to a method for manufacturing a passivated interface between a dielectric material and an III-V compound. The present invention is also directed to a device comprising a low defect interface between a dielectric material and an III-V compound that has improved performance.

Abstract: The present invention provides a method and device for determining, in a non-destructive way, carrier concentration level and junction depth in a semiconductor substrate, independent from each other, during a single measurement.

Abstract: A method and apparatus is provided for self-assembly of micro-components such as microchips onto a carrier substrate, provided with assembly locations for the components. The components are supplied to the carrier by a liquid flow, while a template substrate is arranged facing the carrier. The template is a substrate provided with openings aligned to the assembly locations. The carrier and template are submerged into a tank filled with the liquid, while the liquid flow is supplied to the template side together with the components, so that the components are guided towards the openings by the flow of liquid. Once a component is trapped into an opening of the template, substantially no further liquid flow through the opening is possible, so that following components are guided towards the remaining openings, thereby establishing a fast and reliable self-assembly process.

Abstract: A resonator structure is disclosed. In some embodiments, the resonator structure may include a metal-insulator-metal waveguide comprising a first metal layer, a second metal layer, and an insulating layer between the first metal layer and the second metal layer, wherein the insulating layer comprises a resonating cavity. The resonator structure may further include a mirror formed in the resonating cavity, wherein the mirror comprises at least one nanoscale metallic reflector positioned at least partly in the insulating layer.

Abstract: Disclosed are methods for co-integration of active and passive photonic devices on a planarized silicon-based photonics substrate. In one aspect, a method is disclosed that includes providing a planarized silicon-based photonics substrate comprising a silicon waveguide structure, depositing a dielectric layer over the planarized silicon-based photonics substrate, selectively etching the dielectric layer, thereby exposing at least a portion of the silicon waveguide structure, selectively etching the exposed portion of the silicon waveguide structure to form a template, using the silicon waveguide structure as a seed layer to selectively grow in the template a germanium layer that extends above the dielectric layer, and planarizing the germanium layer to form a planarized germanium layer, wherein the planarized germanium layer does not extend above the dielectric layer.

Abstract: A resistive switching non-volatile memory element is disclosed comprising a resistive switching metal-oxide layer sandwiched between and in contact with a top electrode and a bottom electrode, the resistive switching metal oxide layer having a substantial isotropic non-stoichiometric metal-to-oxygen ratio. For example, the memory element may comprise a nickel oxide resistive switching layer sandwiched between and in contact with a nickel top electrode and a nickel bottom electrode whereby the ratio oxygen-to-nickel of the nickel oxide layer is between 0 and 0.85.

Abstract: A semiconductor device is disclosed. In one aspect, the device has a first and second active layer on a substrate, the second active layer having a higher bandgap than the first active layer, being substantially Ga-free and including at least Al. The device has a gate insulating layer on a part of the second active layer formed by thermal oxidation of a part of the second active layer. The device has a gate electrode on at least a part of the gate insulating layer and a source electrode and drain electrode on the second active layer. The device has, when in operation and when the gate and source electrode are at the same voltage, a two-dimensional electron gas layer between the first and second active layer only outside the location of the gate electrode and not at the location of the gate electrode.

Abstract: An electrostatically actuatable micro electromechanical device is provided with enhanced reliability and lifetime. The electrostatically actuatable micro electromechanical device comprises: a substrate, a first conductor fixed to the top layer of the substrate, forming a fixed electrode, a second conductor fixed to the top layer of the substrate, and a substrate area. The second conductor is electrically isolated from the first conductor and comprises a moveable portion, suspended at a predetermined distance above the first conductor, the moveable portion forming a moveable electrode which approaches the fixed electrode upon applying an actuation voltage between the first and second conductors. The selected substrate surface area is defined as the orthogonal projection of the moveable portion on the substrate between the first and second conductors. In the substrate surface area at least one recess is provided in at least the top layer of the substrate.

Abstract: A semiconductor device is described advantageously making use of the interposer principle. The semiconductor device comprises at least one semiconductor die, a window substrate being an inorganic substrate comprising at least one window-shaped cavity for mounting the at least one semiconductor die, the window substrate having interconnect structures. Furthermore, the at least one semiconductor die is positioned inside the at least one cavity and is connected to the interconnect structures, providing connections to another level of assembly or packaging of the semiconductor device. The invention also relates to a method of manufacturing such a semiconductor device.

Abstract: Device and method for monitoring a plasma in a chamber of a plasma reactor is are disclosed. In one aspect, the method includes measuring plasma parameter data at a surface of a single planar Langmuir probe in contact with the plasma. A biasing capacitor is connected between the single planar Langmuir probe and a DC-bias source. Subsequently a discharge current of the biasing capacitor as a result of the DC-bias is measured, and a probe potential at the single probe during the discharge is measured. The measurements can be used to detect presence and/or thickness of a dielectric film on the probe surface.

Abstract: Disclosed are methods for forming hybrid metal-oxide-semiconductor field effect transistors (MOSFETs) and the hybrid MOSFETS thus obtained. In one embodiment, a method is disclosed that includes providing a first substrate comprising a first region and a second region, providing a second substrate comprising a second semiconductor layer and an insulating layer overlaying the second semiconductor layer, and direct substrate bonding the second substrate to the first substrate, thereby contacting the first region and the second region with the insulating layer. The method further includes selectively removing the second semiconductor layer and the insulating layer in the first region, thereby exposing the first semiconductor layer in the first region, forming a first gate stack of a first MOSFET on the exposed first semiconductor layer in the first region, and forming a second gate stack of a second MOSFET on the second semiconductor layer in the second region.

Abstract: The present disclosure provides a tunnel field effect transistor (TFET) device comprising at least following segments: a highly doped drain region, a lowly doped up to undoped channel region being in contact with the drain region, the channel region having a longitudinal direction, a highly doped source region in contact with the channel region, the contact between the source region and the channel region forming a source-channel interface, a gate dielectric and a gate electrode covering along the longitudinal direction at least part of the source and channel regions, the gate electrode being situated onto the gate dielectric, not extending beyond the gate dielectric, wherein the effective gate dielectric thickness tgd,eff of the gate dielectric is smaller at the source-channel interface than above the channel at a distance from the source-channel interface, the increase in effective gate dielectric thickness tgd,eff being obtained by means of at least changing the physical thickness tgd of the gate dielectri

Abstract: In one aspect, this disclosure provides a substrate for determining the concentration of an analyte within a sample. The substrate includes a conductive region and a recognition layer, the conductive region including at least one particle and having a first surface operatively coupled with the recognition layer, the recognition layer comprising at least one recognition molecule. The distance between the first surface of the conductive region and the recognition molecule is selected such that when the analyte is bound to the recognition layer the combination of the at least one particle and the analyte exhibits at least one of the following effects when radiation is directed through the conductive region and the recognition layer: (i) a particle plasmon effect, (ii) a particle bulk interband absorption, (iii) analyte molecular absorption, and (iv) absorption by the analyte-particle combination.