Patents Assigned to INFINEON
-
Publication number: 20250257469Abstract: A metal component and an electronic device including a metal component is disclosed. In one example, the metal component includes a metallic core material, a first metal layer arranged over the metallic core material, a second metal layer arranged over the first metal layer, and an intermetallic compound layer. The intermetallic compound layer is arranged between the first metal layer and the second metal layer.Type: ApplicationFiled: January 27, 2025Publication date: August 14, 2025Applicant: Infineon Technologies AGInventors: Pei Luan POK, Swee Kah LEE
-
Patent number: 12384272Abstract: A vehicle system includes a vehicle controller configured to detect a parking mode of a vehicle and generate a low-power command based on detecting the parking mode; a collision monitoring system; and a communication interface. The collision monitoring system includes a sensor controller configured to receive the low-power command via the communication interface, enter into a low-power mode, and set the communication interface into an idle communication mode during the low-power mode; a sensor configured to generate a sensor signal based on a measured property; and a processing circuit configured to compute, during the low-power mode, a derivative measurement at a plurality of sampling times based on the sensor signal, and compare each instance of the derivative measurement to a threshold. The sensor controller is configured to transmit a wake-up command to the vehicle controller via the communication interface based on the derivative measurement satisfying the threshold.Type: GrantFiled: December 16, 2022Date of Patent: August 12, 2025Assignee: Infineon Technologies AGInventors: Dan-Alexandru Mocanu, Ilie-Ionut Cristea
-
Patent number: 12386031Abstract: According to a further example implementation, the method comprises measuring magnitude response information relating to an analog baseband signal processing chain of a reception channel of a radar system, determining—based on the measured magnitude response information—at least one value which characterizes at least one frequency limit of the first baseband signal processing chain, and determining a phase response for the baseband signal processing chain based on the at least one value and a model of the baseband signal processing chain. The method also comprises digitizing an output signal from the baseband signal processing chain and digitally processing the digitized output signal, wherein phase equalizing is carried out based on the determined phase response during normal radar operation of the radar system.Type: GrantFiled: June 28, 2022Date of Patent: August 12, 2025Assignee: Infineon Technologies AGInventors: Michael Gerstmair, Michael Petit, Josef Kulmer, Julian Mitterlehner, Dominik Breuer, Alexander Girlinger
-
Patent number: 12386035Abstract: A semiconductor chip comprising at least one transmit channel and/or at least one receive channel for radar signals and also a sequencing circuit is proposed. In this case, the sequencing circuit is configured centrally to determine a sequencing scheme for time-dependent functions of the transmit channel and/or of the receive channel and to drive circuit elements of the transmit channel and/or of the receive channel in accordance with the sequencing scheme.Type: GrantFiled: August 11, 2022Date of Patent: August 12, 2025Assignee: Infineon Technologies AGInventors: Christian Schmid, Rainer Findenig, Bernhard Greslehner-Nimmervoll
-
Patent number: 12386062Abstract: According to various embodiments, a radar system is described including a first radar processing device and a second radar processing device, wherein the first radar processing device is configured to generate radar data and to transmit the radar data partially to the second radar processing device for further processing, wherein the first radar processing device is configured to omit parts of the radar data from the transmission and wherein the second radar processing device is configured to reconstruct the omitted parts using a machine learning model trained to supplement radar data with additional radar data and is configured to further process the transmitted parts of the radar data in combination with the additional radar data.Type: GrantFiled: April 27, 2022Date of Patent: August 12, 2025Assignee: Infineon Technologies AGInventors: Simon Achatz, Maximilian Eschbaumer
-
Patent number: 12388253Abstract: An electrostatic discharge (ESD) protection device includes: a first resistor coupled between a first input terminal of the ESD protection device and a first node of the ESD protection device; a second resistor coupled between the first node and a first output terminal of the ESD protection device; and a first ESD protection component coupled between the first node and a reference voltage terminal of the ESD protection device, where the reference voltage terminal is configured to be coupled to a reference voltage.Type: GrantFiled: July 24, 2023Date of Patent: August 12, 2025Assignee: INFINEON TECHNOLOGIES AGInventors: Anton Gutsul, Joost Adriaan Willemen
-
Patent number: 12388440Abstract: A gate driver has a supply voltage terminal, a bootstrap terminal connected to the supply voltage terminal, a driver having a power input terminal connected to the bootstrap terminal and an output connected to a gate control signal output terminal and configured to generate a gate drive signal at the gate control signal output terminal based on a voltage on the power input terminal, a clamp driver connected to the bootstrap terminal, a clamp transistor connected between a clamp signal input terminal and a reference voltage terminal and having a gate connected to the clamp driver, and an energy harvesting circuit connected between the clamp signal input terminal and the gate of the clamp transistor.Type: GrantFiled: December 28, 2023Date of Patent: August 12, 2025Assignee: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Christian Locatelli, Martina Arosio, Weidong Chu
-
Patent number: 12386462Abstract: An ultrasonic touch sensor includes a touch structure including a touch surface configured to receive a touch, a signal generator configured to generate an excitation, a capacitive ultrasonic transmitter configured to transmit an ultrasonic transmit wave toward the touch structure based on the excitation signal while the touch surface is submerged under the water, a capacitive ultrasonic receiver configured to receive an ultrasonic reflected wave produced by a reflection of the ultrasonic transmit wave at the touch structure while the touch surface is submerged under the water and generate a measurement signal representative of the ultrasonic reflected wave, and a measurement circuit configured to perform a comparison based on the measurement signal and a threshold, and determine whether a no-touch event or a touch event has occurred at the touch surface while the touch surface is submerged under the water based on whether the measurement signal satisfies the threshold.Type: GrantFiled: July 31, 2024Date of Patent: August 12, 2025Assignee: Infineon Technologies AGInventors: Costin Batrinu, Emanuel Stoicescu, Gheorghe-Iulian Chivu, Victor-Valentin Mocanu
-
Patent number: 12389658Abstract: The disclosure relates to a semiconductor die with a transistor device, having a source region, a drain region, a body region including a channel region, a gate region, which includes a gate electrode, next to the channel region, for controlling a channel formation, a drift region between the channel region and the drain region, and a field electrode region with a field electrode formed in a field electrode trench, which extends into the drift region, wherein the channel region extends laterally and is aligned vertically with the gate region, and wherein at least a portion of the channel region is arranged vertically above the field electrode region.Type: GrantFiled: May 13, 2022Date of Patent: August 12, 2025Assignee: Infineon Technologies Austria AGInventor: Thomas Feil
-
Publication number: 20250252043Abstract: An integrated circuit includes an array of flash memory and flash translation layer (FTL) logic coupled to the array and to be coupled to a host device. The FTL logic is configured to receive, from the host device, a write command comprising a first logical address, user data, and an access token and translate the first logical address to a first physical address of the array. In an embodiment, the first physical address has already been programmed. The FTL logic is further to verify the access token as being associated with the first logical address, cause the user data to be programmed to a second physical address of the array, and update at least one logical-to-physical (L2P) mapping table with the second physical address as being mapped to the first logical address.Type: ApplicationFiled: February 6, 2024Publication date: August 7, 2025Applicant: Infineon Technologies LLCInventor: Sergey Ostrikov
-
Publication number: 20250252298Abstract: A method can include, for each row of a nonvolatile memory (NVM) cell array, generating a multiply-accumulate (MAC) result for the row by applying input values on bit lines. Each MAC result comprising a summation of an analog current or voltage that is a function of each input value modified by a corresponding weight value stored by the NVM cells of the row. By operation of at least one multiplexer, one of the rows can be connected to an analog-to-digital converter (ADC) circuit to convert the analog current or voltage of the row into a digital MAC value. A storage element of each NVM cell can be configured to store a weight value that can vary between no less than three different values. Corresponding devices and systems are also disclosed.Type: ApplicationFiled: February 4, 2025Publication date: August 7, 2025Applicant: Infineon Technologies LLCInventors: Prashant Kumar Saxena, Vineet Agrawal, Venkatraman Prabhakar
-
Patent number: 12382652Abstract: A transistor structure that includes multiple heterojunction layer sets, each generating a two-dimensional electron gas (2DEG), such that the transistor structure has a stack of 2DEGs that may be used to conduct between source and drain. A terminal is provided proximate an uppermost 2DEG to control whether the uppermost 2DEG is continuous between a source contact and a source plug. A source plug connects the uppermost 2DEG with the next 2DEG, and a drain plug also connects the uppermost 2DEG with the next 2DEG. Thus, the gate terminal may control the flow of current in sub-surface 2DEGs between the source and drain.Type: GrantFiled: June 7, 2023Date of Patent: August 5, 2025Assignee: Infineon Technologies Canada Inc.Inventors: Marco A Zuniga, Thomas William Macelwee, Vineet Unni, Claudio Andres Canizares
-
Patent number: 12381855Abstract: A network node may receive a control plane message. The control plane message may include an indication that the control plane message is a control plane message, an indication that the control plane message is associated with security, an indication of a security key to be associated with a secure zone (SZ) of an in-vehicle communication network, and an indication of a freshness value. The network node may perform a cryptographic operation for a data plane message associated with the SZ using the security key.Type: GrantFiled: December 13, 2022Date of Patent: August 5, 2025Assignee: Infineon Technologies AGInventors: Alexander Zeh, Donjete Elshani Rama
-
Patent number: 12382677Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, an active cell field in the body, and a plurality of first and second cells in the active cell field. Each cell is electrically connected to the first load terminal structure and to a drift region. Each first cell includes a mesa having a port region electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each second cell includes a mesa having a port region of the opposite conductivity type electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each mesa is spatially confined in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure and has a total extension of less than 100 nm in the direction.Type: GrantFiled: November 5, 2021Date of Patent: August 5, 2025Assignee: Infineon Technologies AGInventors: Anton Mauder, Franz-Josef Niedernostheide, Christian Philipp Sandow
-
Patent number: 12380589Abstract: In an embodiment, a method to evaluate radar images includes providing a first raw radar image and a second raw radar image and determining, whether a reliability criterion is fulfilled. The method further includes using a first coordinate and a second coordinate output by a trained neural network as an estimate of a position of an object if the reliability criterion is fulfilled, the trained neural network using the first raw radar image and the second raw radar image as an input. The method further includes using a third coordinate and a fourth coordinate output by another radar processing pipeline as the estimate of the position of the object if the reliability criterion is not fulfilled, the radar processing pipeline using the first raw radar image and the second raw radar image as an input.Type: GrantFiled: May 27, 2022Date of Patent: August 5, 2025Assignee: Infineon Technologies AGInventors: Lorenzo Servadei, Avik Santra
-
Patent number: 12379666Abstract: A method of generating chip-specific identification code marks on semiconductor chips includes patterning a resist layer over a semiconductor wafer by laser direct image exposure, the patterning including writing chip-specific identification codes into the resist layer over chip areas of the semiconductor wafer. The patterned resist layer is then developed.Type: GrantFiled: April 20, 2023Date of Patent: August 5, 2025Assignee: Infineon Technologies AGInventors: Detlef Hofmann, Heiko Aßmann
-
Patent number: 12379737Abstract: An apparatus includes a calibration circuit operative to produce an error signal indicative of an error associated with a current generator circuit generating a secondary current from a reference current. The secondary current is proportional to the reference current. The calibration circuit derives an adjustment value from the error signal and applies the adjustment value to the current generator circuit. Application of the adjustment value reduces a magnitude of the error signal.Type: GrantFiled: September 28, 2022Date of Patent: August 5, 2025Assignee: Infineon Technologies Austria AGInventors: Sujata Sen, Luca Petruzzi, Aviral Srivastava
-
Patent number: 12381035Abstract: According to one configuration, a fabricator fabricates a core of a circuit component to include magnetic permeable material. The fabricator further produces the circuit component to include multiple electrically conductive paths extending through the core of the magnetic permeable material. In one arrangement, the multiple electrically conductive paths include a first electrically conductive path and a second electrically conductive path. The fabricator fabricates the circuit component and, more specifically, the core of the magnetic permeable material to include at least one cutaway portion operative to reduce inductive coupling between the first electrically conductive path and the second electrically conductive path disposed in the core.Type: GrantFiled: May 12, 2021Date of Patent: August 5, 2025Assignee: Infineon Technologies Austria AGInventors: Luca Peluso, Matthias J. Kasper, Kennith K. Leong, Gerald Deboy
-
Patent number: 12379411Abstract: According to various embodiments, a circuit is described including a plurality of scan flip-flops including a sequence of scan flip-flops, wherein at least some scan flip-flops of the sequence are wrapper scan flip-flops, and including, for each scan flip-flop of at least a subset of the scan flip-flops, at the wrapper scan flip-flop's test input a respective test input circuit configured to, when supplied with a mode control signal having a first value, connect the test input to the output of the preceding wrapper scan flip-flop such that the test input of the flip-flop is supplied with the content of the preceding wrapper scan flip-flop and when supplied with the mode control signal having a second value, connect the test input to an output of a part of the circuit such that the test input of the flip-flop is supplied with a value depending on a test result.Type: GrantFiled: September 25, 2023Date of Patent: August 5, 2025Assignee: Infineon Technologies AGInventor: Alessio Ciarcia
-
Patent number: 12379258Abstract: In accordance with an embodiment, a device includes an interface configured for obtaining at least one measurement signal from a temperature sensor. In a first time interval the at least one measurement signal comprises information about a temperature-dependent voltage difference between a first temperature-dependent voltage at a first diode of the temperature sensor and a second temperature-dependent voltage at a second diode of the temperature sensor. In a second time interval the at least one measurement signal comprises information about a measurement value of a temperature-dependent voltage at a temperature-dependent electrical component of the temperature sensor.Type: GrantFiled: August 2, 2021Date of Patent: August 5, 2025Assignee: Infineon Technologies AGInventors: Christian Jenkner, Daniel Neumaier