Abstract: A circuit includes a switching signal generator and synchronization circuitry configured to determine a first time of a switching period based on a switching signal. The circuit further includes a comparison signal generator configured to generate a comparison signal with a first constant rate of change after the first time. The synchronization circuitry is further configured to determine a second time of the switching period based on when current at the inductive element changes from a positive current to a negative current. The comparison signal generator is further configured to generate the comparison signal with a second constant rate of change after the second time. The circuit further includes a threshold detector configured to compare a value of the comparison signal at the end of a target switching period with a threshold value.

Abstract: An ion movement control apparatus with low pass filter switch, including a digital to analog converter (DAC) connected to a first port and enabled to provide a DAC voltage, an electrode element connected to a second port, the electrode element configured to provide an electrical field for controlling a position of an ion, and a filter switch between the first port and the second port and having a filter leg and a bypass leg in parallel, the filter leg having a filter leg switch and a filter portion between the first port and the second port and selectively coupling the first port through the filter leg to the second port to slow a voltage transient of the DAC voltage to the electrode element, and where the bypass leg has a bypass leg switch that selectively couples the first port directly to the second port.

Abstract: A method of splitting off a semiconductor wafer from a semiconductor bottle includes: forming a separation region within the semiconductor boule, the separation region having at least one altered physical property which increases thermo-mechanical stress within the separation region relative to the remainder of the semiconductor boule; and applying an external force to the semiconductor boule such that at least one crack propagates along the separation region and a wafer splits from the semiconductor boule.

Abstract: A semiconductor device includes a semiconductor die including a first side and an opposing second side, a first metallization layer arranged on the first side, a Ni including layer arranged on the second side, wherein the Ni including layer further includes one or more of Si, Cr and Ti, and a SnSb layer arranged on the Ni comprising layer, wherein an amount of Sb in the SnSb layer is in the range of 2 wt % to 30 wt %.

Abstract: In some examples, a circuit comprises a function unit configured to perform a circuit function, and one or more in situ monitors configured to measure internal data associated with the circuit. The circuit may further comprise a memory configured to store one or more limit values associated with the one or more in situ monitors, and a lifetime model unit configured to determine whether the circuit has reached an end-of-life threshold based on the measured internal data from the one or more in situ monitors and the limit values.

Abstract: A package is disclosed. In one example, the package includes an at least partially electrically conductive carrier having a coupling structure and a reference potential structure which is electrically decoupled from the coupling structure and which is configured to be brought to an electric reference potential during operation of the package, an intermediate structure at the carrier and having an electrically insulating structure oriented towards the carrier and having a mounting structure facing away from the carrier. An electronic component is mounted on the mounting structure and being electrically coupled with the coupling structure. An encapsulant is encapsulating at least part of the intermediate structure, at least part of the electronic component, and part of the carrier so as to expose at least part of the reference potential structure and at least part of the coupling structure.

Abstract: A sensor system may include a magnet arranged such that a linear position of the magnet corresponds to a position of a trigger element on a substantially linear trajectory, and such that an angular position of the magnet corresponds to a selected position of a selection element, the selected position being one of a plurality of selected positions. The sensor system may include a magnetic sensor to determine the position of the trigger element based on a strength of a first magnetic field component and a strength of a second magnetic field component, and determine the selected position of the selection element based on a strength of a third magnetic field component and the strength of the second magnetic field component. The first magnetic field component, the second magnetic field component, and the third magnetic field component may be perpendicular to each other.

Abstract: A wallet including an electronic data storage unit for storing wallet information, and a data interface configured to provide a read access to the electronic data storage unit. A controller of the wallet is configured to control the wallet at a first point in time in a first operating mode, in which there is a restriction for the read access to the wallet information, and to control the wallet at a later second point in time in a second operating mode, in which the restriction to the read access is cancelled. The transition from the first operating mode to the second operating mode is irreversible.

Abstract: A method of producing a semiconductor device includes providing a semiconductor die, providing a metal joining partner, forming a diffusion solderable region by an inkjet metal printing process, forming an assembly to include the diffusion solderable region in between the metal joining partner and the semiconductor die, and performing a diffusion soldering process that forms a soldered joint from the diffusion solderable region in between the semiconductor die and the metal joining partner.

Abstract: The invention relates to a lateral field effect transistor, in particular a HEMT having a heterostructure, in a III/V semiconductor system with a p-type semiconductor being arranged between an ohmic load contact, in particular a drain contact, and a gate contact of the transistor for an injection of holes into a portion of the transistor channel. Further, a recombination zone implemented by a floating ohmic contact is provided for to improve the device performance.

Abstract: A semiconductor device is described. The semiconductor device includes: a semiconductor substrate having an edge, an active area spaced inward from the edge, and an edge termination area laterally surrounding the active area; and a plurality of transistor cells formed in the active area, each transistor cell including a source region of a first conductivity type and a body region of a second conductivity type opposite the first conductivity type. The edge termination area includes a plurality of needle-shaped compensation trenches and is devoid of complete transistor cells. A body doping region of the second conductivity type and that includes the body regions of the transistor cells extends from the active area into the edge termination area. The body doping region in the edge termination area is physically and electrically isolated from the body doping region in the active area.

Abstract: A device for controlling trapped ions includes an ion trap, a plurality of field electrodes configured to control ions in the ion trap, and a controller chip. The controller chip includes at least one delta-sigma digital to analog converter (DS-DAC) module including a DS-DAC circuit configured to receive a digital data stream, convert the digital data stream to analog control voltages, and supply the analog control voltages to the field electrodes.

Abstract: A lateral high-voltage transistor includes a semiconductor substrate, a body region formed by dopant implantation in the semiconductor substrate, the body region having a lateral boundary, a dielectric layer arranged over the semiconductor substrate, and a structured gate layer arranged over the dielectric layer. The structured gate layer overlaps the body region in the semiconductor substrate in a zone between the lateral boundary of the body region and a gate edge of the structured gate layer. The lateral boundary of the body region is a boundary defined by dopant implantation.

Abstract: An apparatus may include an input pin\ and timing control circuitry coupled to the input pin. The timing control circuitry selectively executes one or more timing control functions based on a set of one or more hardware components coupled to the input pin. The set of one or more hardware components are disposed external to the apparatus. A configuration of the set of one or more hardware components determines which of one or more of the multiple timing control functions are enabled.

Abstract: A package is disclosed. In one example, the package comprises a first load terminal, a second load terminal, a power component mounted on the first load terminal, and a logic component electrically conductively mounted on one of the first load terminal. The logic component is the second load terminal and electrically connected with the power component for controlling the power component.

Abstract: A semiconductor device is proposed. An example of the semiconductor device includes a semiconductor body having a first main surface. A trench structure extends into the semiconductor body from the first main surface. The trench structure includes a trench electrode structure and a trench dielectric structure. The trench dielectric structure includes a gate dielectric in an upper part of the trench dielectric structure and a gap in a lower part of the trench dielectric structure. The semiconductor device further includes a body region adjoining the gate dielectric at a sidewall of the trench structure in the upper part of the trench dielectric structure. The gate dielectric extends deeper into the semiconductor body along the sidewall than the body region.

Abstract: A device includes a safety domain having a processing unit and a memory and is configured to provide at least one functionality and to implement one more safety measures for detecting faults. The safety domain is configured to transmit at least one alarm signal indicating one or more detected errors in response to detecting the faults. The device further includes a security domain having a processing unit and a memory and is configured to provide cryptographic services and to obtain alarm signals. The security domain is configured to perform security-related operations in a secure state in response to obtaining an alarm signal from the safety domain.

Abstract: An integrated circuit that is capable of bidirectional communication with an external host device via various communication protocols. In order to determine which communication protocols the incoming signal is using, the integrated circuit further includes an interface detector. When the interface detector determines that the incoming signal represents a portion of a transaction that uses a first communication protocol, the integrated circuit permits the first communication protocol engine to communicate in the transaction. Likewise, when the interface detector determines that the incoming signal represents a portion of a transaction that uses the second communication protocol, the integrated circuit permits the second communication protocol engine to communicate in the transaction. This allows the integrated circuit to detect the protocol regardless of whether one or two package terminals are used in the protocol.

Abstract: A device for controlling trapped ions includes a substrate. An electrode structure is disposed on the substrate, the electrode structure including DC electrodes and RF electrodes of an ion trap configured to trap ions in a space above the substrate. A first device terminal is disposed on the substrate, the first device terminal being connected via a first electrode connection line to a specific DC electrode. Further, a second device terminal is disposed on the substrate, the second device terminal being connected via a second electrode connection line to the specific DC electrode.

Abstract: A device for controlling trapped ions includes a substrate. A first metal layer is disposed over the substrate. An insulating layer is disposed over the first metal layer. A structured second metal layer is disposed over the insulating layer. The structured second metal layer includes an electrode of an ion trap configured to trap ions in a space above the structured second metal layer. The electrode of the structured second metal layer and the first metal layer overlap each other. The device further includes a void space in the insulating layer between the first metal layer and the electrode of the structured second metal layer, the void space including a vacuum at least during operation of the device.