Patents Assigned to INFINEON
  • Device for controlling trapped ions having an electrode circuitry configured for device testing
    Patent number: 12339329
    Abstract: A device for controlling trapped ions includes a substrate. An electrode structure is disposed on the substrate, the electrode structure including DC electrodes and RF electrodes of an ion trap configured to trap ions in a space above the substrate. A first device terminal is disposed on the substrate, the first device terminal being connected via a first electrode connection line to a specific DC electrode. Further, a second device terminal is disposed on the substrate, the second device terminal being connected via a second electrode connection line to the specific DC electrode.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: June 24, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Clemens Roessler, Thomas Ostermann, Norbert Rieser, Johanna Elisabeth Roessler, Siegfried Schmid, Walter Slamnig
  • Method and device for producing an edge structure of a semiconductor component
    Patent number: 12342581
    Abstract: A method for producing an edge structure of a semiconductor component includes: providing a semiconductor body having at least two mutually spaced-apart main faces respectively having an edge, between which edges an edge face extends; and etching a predetermined edge contour by purposely applying a chemical etchant onto the edge face by an etchant jet with simultaneous rotation of the semiconductor body about a rotation axis. The etchant jet is guided with a predetermined jet cross section, while being directed tangentially with respect to the edge face, such that the etchant jet impinges on the edge face only with a part of the jet cross section. A corresponding device for producing an edge structure of a semiconductor component is also described.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: June 24, 2025
    Assignee: Infineon Technologies Bipolar GmbH & Co. KG
    Inventors: Tobias Gamon, Reiner Barthelmess, Uwe Kellner-Werdehausen, Sebastian Sommer
  • Memory device and method for testing the memory device that bypasses memory cells
    Patent number: 12340843
    Abstract: A memory device is provided. The memory device comprises at least one non-volatile memory cell, a write circuit configured to write to the at least one memory cell, and a read circuit configured to read from the at least one memory cell, wherein the memory device is configured to be operable in a test operating mode, in which at least one test path can be tested, and wherein the test path comprises at least a portion of the write circuit and at least a portion of the read circuit, and bypasses the at least one memory cell.
    Type: Grant
    Filed: February 20, 2023
    Date of Patent: June 24, 2025
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kern, Sebastian Kiesel
  • Chopper amplifier circuits and method for operating chopper amplifier circuits
    Patent number: 12341482
    Abstract: A chopper amplifier circuit includes a modulator circuit tuned to a chopper frequency, the modulator circuit being configured, in accordance with the chopper frequency, to convert a voltage into an AC voltage; an amplifier circuit having an inverting input and a non-inverting input for the AC voltage, and having an inverting output and a non-inverting output for providing an amplified AC voltage; and a demodulator circuit tuned to the chopper frequency, the demodulator circuit being configured to convert the amplified AC voltage into an amplified DC voltage. The demodulator circuit is configured to, during different switching phases, couple each of the inverting and non-inverting outputs of the amplifier circuit, both directly and capacitively, to each inverting and non-inverting input of a summing circuit.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: June 24, 2025
    Assignee: Infineon Technologies AG
    Inventors: Mario Motz, Yongjia Li, Andrei-George Roman, Dragos Vocurek
  • Consumable component apparatus
    Patent number: 12340649
    Abstract: A consumable component apparatus including a receptacle region for receiving configured to receive a substance or material which is consumed under the control of a consumer device, an authentication circuit configured to authenticate the consumer device, and a switch coupled to the authentication circuit. The authentication circuit is configured to control the switch in such a way that the consumable component apparatus is activatable only if the consumer device is authenticated by means of the authentication circuit, and that the consumable component apparatus is deactivated if the consumer device is not authenticated by means of the authentication circuit.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: June 24, 2025
    Assignee: Infineon Technologies AG
    Inventors: Peter Laackmann, Markus Gail
  • Method for annealing a gate insulation layer on a wide band gap semiconductor substrate
    Patent number: 12341012
    Abstract: A method for forming a wide band gap semiconductor device is provided. The method includes forming a gate insulation layer on a wide band gap semiconductor substrate and annealing the gate insulation layer using at least a first reactive gas species and a second reactive gas species, wherein the first reactive gas species differs from the second reactive gas species. The method can include forming a gate electrode on the gate insulation layer after annealing the gate insulation layer.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: June 24, 2025
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Gerald Rescher, Michael Stadtmueller
  • Full bridge LLC converter system and method of voltage regulation using a full bridge LLC converter
    Patent number: 12341432
    Abstract: A method of voltage regulation using a full bridge LLC converter includes: selecting a control mode for the full bridge LLC converter based on a nominal output voltage for the full bridge LLC converter, including selecting a first control mode if the nominal output voltage is a first voltage and selecting a second control mode if the nominal output voltage is a second voltage less than the first voltage; in the first control mode, operating the full bridge LLC converter as a full bridge under frequency control; and in the second control mode, operating a first half bridge of the full bridge LLC converter under frequency control and operating a second half bridge of the full bridge LLC converter under duty cycle control with valley switching.
    Type: Grant
    Filed: April 25, 2023
    Date of Patent: June 24, 2025
    Assignee: Infineon Technologies Austria AG
    Inventor: Tae Yong Kim
  • SEMICONDUCTOR DEVICE COMPRISING A CARRIER, A SEMICONDUCTOR DIE AND A C-SHAPED CLIP CONNECTED BETWEEN THEM
    Publication number: 20250201754
    Abstract: A semiconductor device comprising a carrier, a semiconductor die disposed on the carrier and comprising a first contact pad on a first main face remote from the carrier, and a clip. The clip comprises a horizontal portion, a vertical portion, and a bent-back portion connected with the carrier.
    Type: Application
    Filed: December 4, 2024
    Publication date: June 19, 2025
    Applicant: Infineon Technologies AG
    Inventors: Joon Shyan TAN, Thai Kee GAN, Lee Shuang WANG, Azlina KASSIM, Hui Wen GOH, Mei Fen HIEW, Sin Fah YAP
  • SYSTEMS, METHODS, AND DEVICES FOR POWER DOMAIN MANAGEMENT
    Publication number: 20250199697
    Abstract: Systems, methods, and devices provide management of power domains. Methods include activating a first power domain of a memory controller in response to receiving a memory command associated with a storage location coupled to the memory controller, and performing a first portion of a sequence of operations determined based on the memory command, the first portion being performed using a first plurality of processing elements included in the first power domain. Methods further include activating a second power domain of the memory controller based on a timing determined by the sequence of operations, and performing a second portion of the sequence of operations using a second plurality of processing elements included in the second power domain.
    Type: Application
    Filed: December 14, 2023
    Publication date: June 19, 2025
    Applicant: Infineon Technologies LLC
    Inventors: Itzic Cohen, Yair Sofer, Guy Levi, Eran Geyari
  • Method of forming an intermetallic phase layer with a plurality of nickel particles
    Patent number: 12330243
    Abstract: A layer structure includes a first layer including at least one material selected from a first group consisting of nickel, copper, gold, silver, palladium, tin, zinc, platinum, and an alloy of any of these materials; a third layer including at least one material selected from a second group consisting of nickel, copper, gold, palladium, tin, silver, zinc, platinum, and an alloy of any of these materials; and a second layer between the first layer and the third layer. The second layer consists of or essentially consists of nickel and tin. The second layer includes an intermetallic phase of nickel and tin. Methods of forming the layer structure, a chip package and a chip arrangement are also described.
    Type: Grant
    Filed: June 21, 2024
    Date of Patent: June 17, 2025
    Assignee: Infineon Technologies AG
    Inventors: Alexander Heinrich, Alexander Roth, Catharina Wille
  • Electronic circuit and buck converter including the electronic circuit
    Patent number: 12334825
    Abstract: Disclosed is an electronic circuit. The electronic circuit includes a first transistor device, a second transistor device, and a third transistor device, each having a control node and a load path. The electronic circuit further includes a drive circuit. The load paths of the first and second transistor devices are connected in parallel, the load path of the third transistor device is connected in series with the load paths of the first and second transistor devices, and the first transistor device and the second transistor device are integrated in a common semiconductor body. The drive circuit is configured, based on a control signal, to successively switch on the first transistor device and the second transistor device, so that the second transistor device is switched on when the first transistor device is in an on-state.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: June 17, 2025
    Assignee: Infineon Technologies Austria AG
    Inventor: Gerhard Nöbauer
  • Power semiconductor device with dual heat dissipation structures
    Patent number: 12334414
    Abstract: A molded semiconductor package includes: a semiconductor die; a substrate attached to a first side of the semiconductor die; a plurality of leads electrically connected to a second side of the semiconductor die opposite the first side; a heat sink clip thermally coupled to a pad at the second side of the semiconductor die; and a molding compound encapsulating the die, part of the leads, part of the heat sink clip, and at least part of the substrate. The molding compound has a first main side, a second main side opposite the first main side and at which the substrate is disposed, and an edge extending between the first main side and the second main side. The leads protrude from opposing first and second faces of the edge of the molding compound. The heat sink clip protrudes from opposing third and fourth faces of the edge of the molding compound.
    Type: Grant
    Filed: January 8, 2024
    Date of Patent: June 17, 2025
    Assignee: Infineon Technologies AG
    Inventors: Jayaganasan Narayanasamy, Angel Enverga, Chii Shang Hong, Chee Ming Lam, Sanjay Kumar Murugan, Subaramaniym Senivasan
  • Semiconductor die having a sodium stopper in an insulation layer groove and method of manufacturing the same
    Patent number: 12336255
    Abstract: The application relates to a semiconductor die having a semiconductor body including an active region, an insulation layer on the semiconductor body, and a sodium stopper formed in the insulation layer. The sodium stopper is arranged in an insulation layer groove which intersects the insulation layer vertically and extends around the active region. The sodium stopper is formed of a tungsten material that at least partly fills the insulation layer groove. Both the insulation layer groove and the tungsten material extend into the semiconductor body.
    Type: Grant
    Filed: June 1, 2023
    Date of Patent: June 17, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Blank, Christof Altstätter, Ingmar Neumann
  • Transient performance for apparatus with electrically coupled output inductors
    Patent number: 12334827
    Abstract: An apparatus is configured according to a transformer based step down topology is provided. The apparatus includes a first transformer that transfers energy from a primary side of the first transformer to a secondary side of the first transformer for driving a load at the secondary side. The apparatus includes a first inductor and a second inductor electrically coupled at the secondary side. The apparatus includes a primary side directional conducting element and a secondary side directional conducting element configured to perform a first phase of transferring the energy through the first inductor and a second phase of transferring the energy through the second inductor. The first inductor induces the second inductor to transfer energy during the first phase and the second inductor induces the first inductor to transfer energy during the second phase.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: June 17, 2025
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Yong Zhou, Danny Clavette, Stephen Roy Pullen
  • Timer circuit
    Patent number: 12334822
    Abstract: A timer circuit including a ramp voltage generator configured to generate a ramp voltage, a comparator coupled on its input side to the ramp voltage generator to receive the ramp voltage and configured to compare the ramp voltage with a switching threshold, and a voltage pulse generating circuit configured to generate a reset signal as a response to a received output signal of the comparator, wherein the reset signal has a shorter time duration than an intrinsic reset time duration of the comparator.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: June 17, 2025
    Assignee: Infineon Technologies AG
    Inventor: Julia Richter
  • Package with pad having open notch
    Patent number: 12334458
    Abstract: A package is disclosed. In one example, the package comprises an electronic component having a first main surface with an electrically conductive first pad. The first pad has an open notch, and a spacer body mounted on the first pad and bridging at least part of the open notch.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: June 17, 2025
    Assignee: Infineon Technologies AG
    Inventor: Adrian Lis
  • Devices and methods for authentication
    Patent number: 12335413
    Abstract: A device has a receiver designed to receive a data packet from a communication partner, a data processor to process the data packet in order to obtain a secret value, a transmitter designed to transmit a transmit message having information based on the secret value to the communication partner, and an authentication device designed to receive a challenge message and to use the secret value to create a response message, wherein the transmitter is designed to create the transmit message to include the response message.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: June 17, 2025
    Assignee: Infineon Technologies AG
    Inventors: Thomas Poeppelmann, Armin Krieg
  • Magnetic angle sensor with symmetrical geometric arrangement
    Patent number: 12332090
    Abstract: The herein disclosed innovative concept concerns a magnetic angle sensor and a method for operating the same. The sensor includes a magnetoresistive arrangement and a magnetic source being configured to be movable relative to the magnetoresistive arrangement. The magnetoresistive arrangement includes a first magnetoresistive element configured to generate a first output signal, a second magnetoresistive element configured to generate a second output signal, and a third magnetoresistive element configured to generate a third output signal. The first, second and third magnetoresistive elements are oriented relative to each other such that they form a symmetrical geometric arrangement with equal angular distances between each other.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: June 17, 2025
    Assignee: Infineon Technologies AG
    Inventors: Joo Il Park, Se Hwan Kim, Klaus Grambichler, Gernot Binder
  • Electronic devices including vent openings and associated methods
    Patent number: 12334405
    Abstract: An electronic device and method is disclosed. In one example, the electronic device includes a solderable surface and at least one surface opening arranged in the solderable surface. The electronic device further includes an encapsulation material, encapsulating at least one electronic component of the electronic device, and at least one vent opening arranged in an area of the surface opening and extending through the encapsulation material.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: June 17, 2025
    Assignee: Infineon Technologies AG
    Inventors: Michael Stadler, Thomas Bemmerl
  • Ultrasonic transducer
    Patent number: 12326998
    Abstract: An ultrasonic transducer includes at least one ultrasonic transducer element, a semiconductor chip that includes the ultrasonic transducer element, and a housing. The semiconductor chip is arranged in the housing. The semiconductor chip is embedded in a dimensionally stable encapsulation, wherein a contact surface of the dimensionally stable encapsulation is configured for acoustically coupling the ultrasonic transducer to a casing. Additionally, an ultrasonic transducer system and a method for fitting the ultrasonic transducer or ultrasonic transducer system are provided.
    Type: Grant
    Filed: March 23, 2023
    Date of Patent: June 10, 2025
    Assignee: Infineon Technologies AG
    Inventors: Klaus Elian, Matthias Eberl, Horst Theuss, Rainer Markus Schaller, Fabian Merbeler