Patents Assigned to INFINEON
  • Patent number: 12379411
    Abstract: According to various embodiments, a circuit is described including a plurality of scan flip-flops including a sequence of scan flip-flops, wherein at least some scan flip-flops of the sequence are wrapper scan flip-flops, and including, for each scan flip-flop of at least a subset of the scan flip-flops, at the wrapper scan flip-flop's test input a respective test input circuit configured to, when supplied with a mode control signal having a first value, connect the test input to the output of the preceding wrapper scan flip-flop such that the test input of the flip-flop is supplied with the content of the preceding wrapper scan flip-flop and when supplied with the mode control signal having a second value, connect the test input to an output of a part of the circuit such that the test input of the flip-flop is supplied with a value depending on a test result.
    Type: Grant
    Filed: September 25, 2023
    Date of Patent: August 5, 2025
    Assignee: Infineon Technologies AG
    Inventor: Alessio Ciarcia
  • Patent number: 12382678
    Abstract: A transistor arrangement is disclosed. The transistor arrangement includes a first transistor device and a second transistor device. The first transistor device and the second transistor device are connected in series and integrated in a common semiconductor body. The first transistor device is a lateral superjunction transistor device and is integrated in a first device region of the semiconductor body. The second transistor device is a lateral transistor device and is integrated in at least one second device region of the semiconductor body. The at least one second device region is spaced apart from the first device region.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: August 5, 2025
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Rolf Weis, Franz Hirler, Katarzyna Kowalik-Seidl, Marco Mueller, Anthony Sanders
  • Patent number: 12381381
    Abstract: A sensor device contains a busbar, a dielectric shell arranged over the busbar, a dielectric layer arranged over the busbar, and a sensor chip arranged within the dielectric shell, wherein the sensor chip is configured to detect a magnetic field induced by an electric current flowing through the busbar.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: August 5, 2025
    Assignee: Infineon Technologies AG
    Inventors: Rainer Markus Schaller, Volker Strutz, Ronak Kalhor-Witzel, Hansjoerg Walter Kuemmel
  • Patent number: 12381499
    Abstract: A motor controller includes a measurement interface configured to measure a mechanical angle of a shaft driven by a motor and a rotational speed of the shaft, and generate a speed feedback signal representative of the rotational speed, a speed regulator, and a current regulator. The speed regulator includes an error component configured to generate a speed error signal based on a difference between a speed reference signal and the speed feedback signal; a proportional integral controller configured to, based on the speed error signal, regulate a torque reference value that is configured to sustain a speed reference value; and a load torque ripple compensator configured to apply a torque feedforward function to reduce a load torque ripple in the torque reference value. The current regulator is configured to drive motor currents of the motor for generating a torque corresponding to the torque reference value.
    Type: Grant
    Filed: August 30, 2023
    Date of Patent: August 5, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Brendan Murray, Lei Han
  • Patent number: 12374632
    Abstract: A semiconductor device includes an active region and a trapping region positioned peripherally with respect to the active region, the trapping region presenting trapping apertures permitting the passage of particles, the trapping apertures being in fluid communication with at least one trapping chamber for trapping the particles. A method for manufacturing the semiconductor devices from one semiconductor wafer presents semiconductor device regions to be singulated along a dicing portion line.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: July 29, 2025
    Assignee: Infineon Technologies AG
    Inventors: Gunther Mackh, Martin Brandl, Bernhard Drummer
  • Patent number: 12375081
    Abstract: A gate driver device includes a first field effect transistor and a first driver circuit. The first field effect transistor includes a first gate electrode and a first backgate structure. The first driver circuit supplies a first backgate drive signal to the first backgate structure.
    Type: Grant
    Filed: February 12, 2024
    Date of Patent: July 29, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Dirk Priefert, Matteo Albertini, Remigiusz Viktor Boguszewicz
  • Patent number: 12374994
    Abstract: An apparatus as discussed herein can be configured to include a first bridge circuit operative to receive an input voltage supplied by an input voltage source. An inductor in the apparatus also receives the input voltage. The apparatus can be configured to include a second bridge circuit. The inductor provides coupling of the input voltage source to the second bridge circuit. The second bridge circuit produces an output voltage to power a load.
    Type: Grant
    Filed: January 5, 2023
    Date of Patent: July 29, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Kevin Tomas Manez, Juan Miquel Martinez Sanchez
  • Patent number: 12375049
    Abstract: A balanced power amplifier includes a first power amplifier configured to apply a first gain having a first predetermined magnitude and a first programmable phase adjustable phase to generate a first amplified signal, the first programmable phase being adjustable to either a first phase or to a second phase that is 180° phase shifted relative to the first phase; a second power amplifier configured to apply a second gain having a second predetermined magnitude and a second programmable phase to generate a second amplified signal, the second programmable phase being adjustable to either the first phase or to the second phase; and a 90° hybrid coupler configured to receive the first amplified signal and the second amplified signal and generate and output a first output signal or a second output signal based on a combination of the first amplified signal and the second amplified signal.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: July 29, 2025
    Assignee: Infineon Technologies AG
    Inventor: Vincenzo Fiore
  • Patent number: 12372633
    Abstract: A radar monolithic microwave integrated circuit includes a radio frequency (RF) input configured to receive an RF signal comprising a plurality of frequency ramps; a baseband processing circuit configured to convert the RF signal into a baseband signal comprising a plurality of analog signal segments each corresponding to a different frequency ramp; an analog-to-digital converter configured to convert the plurality of analog signal segments into a plurality of respective digital signal segments, wherein each digital signal segment of the plurality of respective digital signal segments comprises a plurality of digital samples corresponding to a respective analog signal segment; and an encoder configured to receive a single digital signal segment and compress the plurality of digital samples of the single digital signal segment based on a data compression that has a defined correlation with a windowing function to generate compressed radar data corresponding to the single digital signal segment.
    Type: Grant
    Filed: January 24, 2023
    Date of Patent: July 29, 2025
    Assignee: Infineon Technologies AG
    Inventor: Stefan Schmalzl
  • Patent number: 12374640
    Abstract: A device for trapping ions includes: a substrate having a metal layer structure; and at least one ion trap configured to trap ions in a space over the substrate. The metal layer structure is a multi-layer metal structure that includes: a top metal layer having one or more electrodes forming part of the at least one ion trap; a redistribution metal layer having wiring for connecting the one or more electrodes; a first insulating layer arranged between the top metal layer and the redistribution layer and having one or more voids; and one or more connection elements arranged in the one or more voids that connect the wiring from the redistribution metal layer with the one or more electrodes in the top metal layer.
    Type: Grant
    Filed: March 4, 2024
    Date of Patent: July 29, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Clemens Roessler, Silke Auchter, Martin Gruber, Johanna Elisabeth Roessler
  • Patent number: 12374661
    Abstract: A power module includes: a first substrate having a patterned first metallization; a second substrate vertically aligned with the first substrate and having a patterned second metallization that faces the patterned first metallization; first vertical power transistor dies having a drain pad attached to a first island of the patterned first metallization and a source pad electrically connected to a first island of the patterned second metallization via first spacers; and second vertical power transistor dies having a source pad electrically connected to the first island of the patterned first metallization via second spacers. A first subset of the second vertical power transistor dies has a drain pad attached to a second island of the patterned second metallization. A second subset of the second vertical power transistor dies has a drain pad attached to a third island of the patterned second metallization. A method of producing the module is described.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: July 29, 2025
    Assignee: Infineon Technologies AG
    Inventors: Adrian Lis, Ewald Guenther, Thomas Schmid
  • Patent number: 12376334
    Abstract: A semiconductor device includes a semiconductor body having first and second opposing surfaces in a vertical direction, and transistor cells at least partly integrated in the semiconductor body. Each transistor cell includes first and second source regions, first and second body regions, a drift region separated from the respective source region by the corresponding body region, a first gate electrode, and a control electrode. The drift region is arranged between the first and the second body region in a horizontal direction that is perpendicular to the vertical direction and extends from the first surface into the semiconductor body in the vertical direction. The first gate electrode is configured to provide a control signal for switching the transistor cell. The control electrode is configured to provide a control signal for controlling a JFET formed by the first body region, the drift region, and the second body region.
    Type: Grant
    Filed: October 14, 2022
    Date of Patent: July 29, 2025
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Katarzyna Kowalik-Seidl, Armin Tilke, Markus Wiesinger
  • Patent number: 12372780
    Abstract: A microelectromechanical systems (MEMS) mirror package assembly includes: a MEMS wafer including a stator portion and a rotor portion that includes a MEMS mirror configured to rotate about an axis, wherein the MEMS mirror is suspended over a back cavity, wherein the MEMS wafer defines a first portion of the back cavity; a spacer wafer, wherein the backside of the spacer wafer is bonded to the frontside of the MEMS wafer, wherein the spacer wafer defines a first portion of a front cavity arranged over the MEMS mirror; a transparent cover wafer, wherein the backside of the transparent cover wafer is bonded to the frontside of the spacer wafer, wherein the transparent cover wafer includes a transparent dome structure arranged over the MEMS mirror and defining a second portion of the front cavity. The center of the MEMS mirror is arranged substantially at a vertex of the transparent dome structure.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: July 29, 2025
    Assignee: Infineon Technologies AG
    Inventors: Andre Brockmeier, Ulf Bartl, Kurt Sorschag
  • Patent number: 12373808
    Abstract: An electronic device is provided. The electronic device may include at least one electronic circuit configured to selectively provide at least one function, an interface configured to receive from a source external to the electronic device instructions including a device identification and at least one usage measurement parameter, and a secure element configured to receive the instructions from the interface, to process the instructions, and to modify the at least one function based on a processing result.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: July 29, 2025
    Assignee: Infineon Technologies AG
    Inventors: Stephen Hanna, Theodore Varelas
  • Publication number: 20250240890
    Abstract: A method of embedding an embeddable object into a stacked substrate is provided. The method may include forming a stacked substrate including a first layer and a second layer disposed over the first layer, and embedding material disposed between the first layer and the second layer. The embeddable object is disposed into a recess of the stacked substrate. A portion of the embedding material is transferred from a high viscosity or solid state into a low viscosity state so that at least a portion of the embedding material flows into the recess to laterally fix the embeddable object within the recess to the stacked substrate.
    Type: Application
    Filed: January 21, 2025
    Publication date: July 24, 2025
    Applicant: Infineon Technologies AG
    Inventors: Thomas GEBHARD, Toni SALMINEN, Mahadi-Ul HASSAN
  • Patent number: 12368374
    Abstract: A monolithic half-bridge gate driver includes a phase node terminal configured to be coupled to a phase node to which a high-side transistor and a low-side transistor of a half-bridge are coupled; a diode comprising an anode and a cathode, wherein the cathode is coupled to the phase node terminal; and a comparator comprising a first input terminal coupled to the anode of the diode for receiving a measurement value indicative of a phase voltage at the phase node terminal, a second input terminal coupled to a threshold source for receiving a threshold, and an output terminal configured to output a comparison result indicating whether the measurement value satisfies the threshold. The phase node terminal is configured to be connected to a high-side supply potential by the high-side transistor, and is configured to be connected to a low-side supply potential by the low-side transistor.
    Type: Grant
    Filed: July 20, 2023
    Date of Patent: July 22, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Diego Raffo, Weidong Chu, Christian Locatelli
  • Patent number: 12368052
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of patterns of metal structures in a dielectric inorganic substrate wafer. The metal structures are accommodated in recesses of the dielectric inorganic substrate wafer and at least partly connect through the dielectric inorganic substrate. The method further includes providing a semiconductor wafer comprising a front side and a backside, wherein a plurality of electrodes is disposed on the front side of the semiconductor wafer. The front side of the semiconductor wafer is bonded to the dielectric inorganic substrate wafer to form a composite wafer, wherein the plurality of patterns of metal structures is connected to the plurality of electrodes. The composite wafer is separated into composite chips.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: July 22, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Christian Fachmann, Barbara Angela Glanzer, Andreas Riegler
  • Patent number: 12368520
    Abstract: A method for determining a nonlinearity characteristic of a receiver path includes generating a set of N×M digital samples by repeating N times selecting an scaling factor from a set of N scaling factors, generating a version of a test signal, the version of the test signal corresponding to a test signal scaled by the respective scaling factor, processing the respective version of the test signal in at least a part of the receiver path to generate a respective processed signal, and storing M digital samples corresponding to the respective processed signal. Fourier-transformed data are generated using at least a portion of the set of N×M digital samples and a nonlinearity characteristic of the receiver path is determined based on the Fourier-transformed data.
    Type: Grant
    Filed: October 10, 2023
    Date of Patent: July 22, 2025
    Assignee: Infineon Technologies AG
    Inventors: Oliver Lang, Matthias Wagner, Esmaeil Kavousi Ghafi, Andreas Schwarz
  • Patent number: 12368448
    Abstract: A digital microphone includes a log amplifier having an input for receiving an analog signal; an analog-to-digital converter (ADC) coupled to the log amplifier; a digital low-pass filter coupled to the ADC; a digital decompression component coupled to the digital low-pass filter; and a predictor filter coupled to the digital decompression component, the predictor filter having an output for generating a digital signal. The digital low-pass filter is a positive group delay filter and the predictor filter is a negative group delay filter. The digital microphone has an improved Signal-to-Noise Ratio (SNR) due to filtering, but without increasing overall group delay.
    Type: Grant
    Filed: March 24, 2023
    Date of Patent: July 22, 2025
    Assignee: Infineon Technologies AG
    Inventors: Dietmar Straeussnigg, Simon Grünberger
  • Patent number: 12369253
    Abstract: This disclosure includes multiple assemblies, sub-assemblies, etc., as well as one or more methods of fabricating same. For example, a first assembly includes a first circuit board. The first circuit board further includes first connector elements disposed on a first edge of the first circuit board and second connector elements disposed on a second edge of the first circuit board. The first edge may be disposed substantially opposite the second edge on the first circuit board. The apparatus may further include first circuitry affixed to the first circuit board. The first edge of the first circuit board aligns with a first axial end of the first circuitry and the second edge of the first circuit board aligns with a second axial end of the first circuitry. The first assembly is used to fabricate a second assembly.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: July 22, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Eung San Cho, Danny Clavette