Patents Assigned to Infineon Technologies AG
  • Patent number: 11404370
    Abstract: A semiconductor device is provided. In an embodiment, the semiconductor device comprises a control region, a first power region, a second power region, an isolation region and/or a short circuit structure. The control region comprises a control terminal. The first power region comprises a first power terminal. The second power region comprises a second power terminal. The isolation region is between the control region and the first power region. The short circuit structure extends from the first power region, through the isolation region, to the control region. The short circuit structure is configured to form a low-resistive connection between the control region and the first power region during a failure state of the semiconductor device.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: August 2, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Basler, Andreas Huerner, Caspar Leendertz, Dethard Peters
  • Patent number: 11405027
    Abstract: In accordance with an embodiment a circuit includes: a plurality of delay elements coupled in series, each delay element including an input node and an output node; a multiplexer having inputs coupled to the output node of each delay element of the plurality of delay elements; and a time measurement circuit including a time amplifier having an input coupled to an output of the multiplexer, and a counter coupled to an output of the time amplifier.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: August 2, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Stefano Bonomi, Nicolo Zilio
  • Patent number: 11404392
    Abstract: A molded semiconductor module include: a semiconductor die attached to a main surface of a metal block. The die has a metal contact pad at a side of the die facing away from the metal block. A metal terminal has a contact region attached to the metal contact pad of the die, and a distal end region that joins the contact region and is bent upward in a direction away from the metal block such that the distal end region has a free end which terminates at a further distance from the metal block than the contact region. A molding compound encapsulates the die and covers the contact region of the metal terminal. The distal end region of the metal terminal protrudes through a surface of the molding compound that faces a same direction as the side of the die with the metal contact pad.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: August 2, 2022
    Assignee: Infineon Technologies AG
    Inventor: Ivan Nikitin
  • Publication number: 20220238481
    Abstract: An electronic module is disclosed. In one example, the electronic module includes a first substrate, a first dielectric layer on the first substrate, at least one electronic chip, which is mounted with a first main surface directly or indirectly on partial region of the first dielectric layer, a second substrate over a second main surface of the at least one electronic chip, and an electrical contacting for the electric contact of the at least one electronic chip through the first dielectric layer. The first adhesion layer on the first substrate extends over an area, which exceeds the first main surface.
    Type: Application
    Filed: April 18, 2022
    Publication date: July 28, 2022
    Applicant: Infineon Technologies AG
    Inventors: Petteri PALM, Thorsten SCHARF, Ralf WOMBACHER
  • Publication number: 20220239267
    Abstract: A gray zone prevention circuit includes: a first gain stage circuit including a first input terminal and a first output terminal, the first gain stage circuit amplifies a feedback signal received at the first input terminal and generates an amplified signal at the first output terminal; a second gain stage circuit including a terminal that is coupled to the first output terminal for receiving the amplified signal and a second output terminal, where the second gain stage circuit is configured to generate a monitored signal based on the amplified signal; a feedback circuit coupled between the second output terminal and the first input terminal and configured to convert the monitored signal into the feedback signal; and a comparator circuit including a monitoring node coupled to the first output terminal for receiving the amplified signal, wherein the comparator circuit is configured to monitor the monitored signal indirectly via the amplified signal.
    Type: Application
    Filed: January 26, 2021
    Publication date: July 28, 2022
    Applicant: Infineon Technologies AG
    Inventors: Christoph SCHROERS, Carlos Humberto GARCIA ROJAS, Elisa SANFILIPPO, Veikko SUMMA
  • Publication number: 20220236123
    Abstract: A stress sensor includes a semiconductor substrate with a first transistor arrangement and a second transistor arrangement. The first transistor arrangement includes a first transistor with a first source-drain channel region and a second transistor with a second source-drain channel region. The first transistor and the second transistor are aligned relative to each other such that the current flow directions in the first and the second source-drain channel regions are opposite to each other. The second transistor arrangement includes a third transistor with a third source-drain channel region and a fourth transistor with a fourth source-drain channel region. The third transistor and the fourth transistor are aligned relative to each other such that the current flow directions in the third and the fourth source-drain channel regions are opposite to each other. The stress sensor generates a gradient-compensated output signal used to determine a mechanical stress acting on the semiconductor substrate.
    Type: Application
    Filed: January 25, 2022
    Publication date: July 28, 2022
    Applicant: Infineon Technologies AG
    Inventor: Mario MOTZ
  • Publication number: 20220238413
    Abstract: A double sided cooling module that includes a leadframe with a top Direct Copper Bonded (DCB) substrate and two or more power transistor submodules. Each one of the power transistor submodules includes a bottom DCB substrate, a spaced-apart row of first wires attached to a top metal layer of the bottom DCB substrate proximate to the first side of the top metal layer, a semiconductor die having a bottom side load path contact attached to a top surface of a die pad portion of the top metal layer, a top side control contact electrically coupled via at least one bond wire to a top surface of a control pad portion of the top metal layer, and an electrically conductive and thermally conductive spacer that is attached to the top side load path contact and to a bottom metal layer of the top DCB substrate. At least one of the first wires is attached to the control pad portion of the top metal layer and to a bottom metal layer of the top DCB substrate.
    Type: Application
    Filed: January 22, 2021
    Publication date: July 28, 2022
    Applicant: Infineon Technologies AG
    Inventor: Andreas GRASSMANN
  • Patent number: 11398472
    Abstract: An RC IGBT with an n-barrier region in a transition section between a diode section and an IGBT section is presented.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: July 26, 2022
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Roman Baburske, Frank Dieter Pfirsch, Alexander Philippou, Christian Philipp Sandow
  • Patent number: 11397239
    Abstract: In an embodiment, a method of operating a radar includes: transmitting a radiation pulse with the radar during an active mode; asserting a sleep flag after transmitting the radiation pulse; turning off a crystal oscillator circuit of the radar after the sleep flag is asserted; clocking a counter of the radar with a low power oscillator during a low power mode after the sleep flag is asserted; asserting a timer flag when the counter reaches a first threshold; and transitioning into the active mode after the timer flag is asserted.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: July 26, 2022
    Assignee: Infineon Technologies AG
    Inventors: Reinhard-Wolfgang Jungmaier, Christoph Rumpler, Saverio Trotta
  • Publication number: 20220230930
    Abstract: A package is disclosed. In one example, the package comprises a carrier comprising a thermally conductive and electrically insulating layer, a laminate comprising a plurality of connected laminate layers, an electronic component mounted between the carrier and the laminate. An encapsulant is at least partially arranged between the carrier and the laminate and encapsulating at least part of the electronic component.
    Type: Application
    Filed: January 13, 2022
    Publication date: July 21, 2022
    Applicant: Infineon Technologies AG
    Inventor: Andreas GRASSMANN
  • Publication number: 20220230919
    Abstract: A method of manufacturing a semiconductor package is provided. The method may include singulating a wafer including a plurality of dies fixed to an auxiliary carrier to generate dies having released side surfaces, covering at least the side surfaces of the dies with a passivation layer using a deposition process at a temperature below the melting temperature of the auxiliary carrier, keeping a gap between the passivation layers at the side surfaces of adjacent dies of the plurality of dies.
    Type: Application
    Filed: January 13, 2022
    Publication date: July 21, 2022
    Applicant: Infineon Technologies AG
    Inventors: Fabian CRAES, Wolfgang LEHNERT, Maik LOHMANN, Harry Walter SAX
  • Patent number: 11393115
    Abstract: An example method for performing depth measurements with an image sensor comprises, for at least a first pixel, performing one or more continuous-wave phase measurements for the first pixel and performing a coded-modulation measurement for the first pixel. The method further comprises determining a mask value for the first pixel, based on the coded-modulation measurement, and applying the mask value to a distance value calculated from the one or more continuous-wave phase measurements, to obtain a masked distance value for the first pixel that has no ambiguity due to phase wrapping.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: July 19, 2022
    Assignee: Infineon Technologies AG
    Inventors: Hannes Plank, Armin Schoenlieb
  • Patent number: 11393743
    Abstract: A semiconductor device includes a conductive frame comprising a die attach surface that is substantially planar, a semiconductor die comprising a first load on a rear surface and a second terminal disposed on a main surface, a first conductive contact structure disposed on the die attach surface, and a second conductive contact structure on the main surface. The first conductive contact structure vertically extends past a plane of the main surface of the semiconductor die. The first conductive contact structure is electrically isolated from the main surface of the semiconductor die by an electrical isolation structure. An upper surface of the electrical isolation structure is below the main surface of the semiconductor die.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: July 19, 2022
    Assignee: Infineon Technologies AG
    Inventors: Stuart Cardwell, Chee Yang Ng, Josef Maerz, Clive O'Dell, Mark Pavier
  • Patent number: 11394378
    Abstract: An integrated circuit comprises a power switch comprising a current path and a current sense node; and a temperature sense circuit internally coupled between the current path and the current sense node.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: July 19, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Tomas Manuel Reiter, Georg Schinner, Frank Wolter
  • Patent number: 11391791
    Abstract: A sensor device comprises an electrically conductive chip carrier, wherein the chip carrier comprises an auxiliary structure, wherein the auxiliary structure comprises a first precalibration current terminal and a second precalibration current terminal, a magnetic field sensor chip arranged on a mounting surface of the chip carrier, wherein the magnetic field sensor chip comprises a sensor element, wherein the shape of the auxiliary structure is embodied such that an electrical precalibration current flowing from the first precalibration current terminal to the second precalibration current terminal through the auxiliary structure induces a predefined precalibration magnetic field at the location of the sensor element, wherein during measurement operation of the precalibrated sensor device, no precalibration current flows between the first precalibration current terminal and the second precalibration current terminal.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: July 19, 2022
    Assignee: Infineon Technologies AG
    Inventors: Gernot Binder, Riccardo Dapretto, Diego Lunardini, Mario Motz, Volker Strutz
  • Patent number: 11394428
    Abstract: According to one embodiment a circuit comprises a supply pin operable to receive a supply voltage, a non-volatile memory for storing one or more parameters, and a Near Field Communication (NFC) transceiver that is operable to receive data representing the one or more parameters. The circuit is operable to deactivate the NFC transceiver in response to receiving the supply voltage at the supply pin.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: July 19, 2022
    Assignee: Infineon Technologies AG
    Inventors: Doris Keitel-Schulz, Renate Angelika Muehlbauer, Matthias Schneider, Qi Zhu, Dieter Zipprick
  • Patent number: 11394194
    Abstract: A power inverter includes a bridge circuit including a first half-bridge and a second half-bridge, each half-bridge including a high-side device and a low-side device, and a gate driver circuit connected with each gate of the high-side device and low-side power device of the first and second half-bridges and operable to provide each gate with a respective voltage to control operation of the respective power device. The gate driver is operable to provide a first voltage which is higher than a first threshold voltage of the respective power device, and a second voltage which is higher than a surge threshold of the respective power device. The surge threshold is higher than the first threshold and defines the onset of a surge current operation area of the respective power device at which the power device becomes conducts a surge current that is larger than the rated current of the device.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: July 19, 2022
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Thomas Basler, Hans-Joachim Schulze
  • Patent number: 11393784
    Abstract: A method for forming semiconductor devices includes attaching a glass structure to a wide band-gap semiconductor wafer having a plurality of semiconductor devices. The method further includes forming at least one pad structure electrically connected to at least one doping region of a semiconductor substrate of the wide band-gap semiconductor wafer, by forming electrically conductive material within at least one opening extending through the glass structure.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: July 19, 2022
    Assignee: Infineon Technologies AG
    Inventors: Roland Rupp, Alexander Breymesser, Andre Brockmeier, Carsten von Koblinski, Francisco Javier Santos Rodriguez, Ronny Kern
  • Patent number: 11393714
    Abstract: In a method for producing a buried cavity in a semiconductor substrate, trenches are produced in a surface of a semiconductor substrate down to a depth that is greater than cross-sectional dimensions of the respective trench in a cross section perpendicular to the depth, wherein a protective layer is formed on sidewalls of the trenches. Isotropic etching through bottom regions of the trenches is carried out. After carrying out the isotropic etching, the enlarged trenches are closed by applying a semiconductor epitaxial layer to the surface of the semiconductor substrate.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: July 19, 2022
    Assignee: Infineon Technologies AG
    Inventors: Andre Roeth, Boris Binder, Thoralf Kautzsch, Uwe Rudolph, Maik Stegemann, Mirko Vogt
  • Patent number: 11393742
    Abstract: A semiconductor flip-chip package includes a substrate having a first main face, a second main face opposite to the first main face, and one or more conductive structures disposed on the first main face, one or more pillars disposed on at least one of the conductive structures, a semiconductor die having one or more contact pads on a main face thereof, the semiconductor die being connected to the substrate so that at least one of the contact pads is connected with one of the pillars, and an encapsulant disposed on the substrate and the semiconductor die.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: July 19, 2022
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Irmgard Escher-Poeppel, Klaus Pressel, Bernd Rakow