Abstract: A circuit is provided that comprises a transformer having a first coil, which is arranged on a substrate, a second coil, which is arranged above the first coil on the substrate, and a dielectric between the first coil and the second coil. The circuit furthermore comprises a resonant circuit, which is couplable to the first coil and/or the second coil to form a resonant loop, wherein a measure of a characteristic frequency of the resonant loop and/or a measure of a power consumption of the resonant loop is able to be tapped off at an output of the resonant circuit. A corresponding method is also provided.

Abstract: A method is disclosed. In one example, the method includes bonding a first panel of a first material to a base panel in a first gas atmosphere, wherein multiple hermetically sealed first cavities encapsulating gas of the first gas atmosphere are formed between the first panel and the base panel. The method further includes bonding a second panel of a second material to at least one of the base panel and the first panel, wherein multiple second cavities are formed between the second panel and the at least one of the base panel and the first panel.

Abstract: An ESD protection device may include: a first vertically integrated ESD protection structure comprising a first semiconductor portion, a first contact region disposed on a first side of the first semiconductor portion and a first terminal exposed on a second side of the first semiconductor portion opposite the first side of the first semiconductor portion, a second vertically integrated ESD protection structure comprising a second semiconductor portion, a second contact region disposed on a first side of the second semiconductor portion and a second terminal exposed on a second side of the second semiconductor portion opposite the first side of the second semiconductor portion, an electrical connection layer, wherein the first vertically integrated ESD protection structure and the second vertically integrated ESD protection structure are disposed on the electrical connection layer laterally separated from each other and are electrically connected with each other anti-serially via the electrical connection lay

Abstract: A semiconductor device includes a substrate comprising an antenna and a conductive feature; an integrated circuit (IC) die attached to the substrate and comprising a radio frequency (RF) circuit; and a flexible circuit integrated with the substrate, where the flexible circuit is electrically coupled to the IC die and the substrate, a first portion of the flexible circuit being disposed between opposing sidewalls of the substrate, a second portion of the flexible circuit extending beyond the opposing sidewalls of the substrate, the second portion of the flexible circuit comprising an electrical connector at a distal end.

Abstract: A redundancy system includes a first computational device and a second computational device each configured to receive at least one input and to generate a first output and a second output, respectively, based on the at least one input; a random sequence generator configured to generate a random bit sequence; a random delay selector configured to determine a random delay based on the random bit sequence; a first random delay circuit configured to delay outputting the at least one input to the first computational device based on the random delay; a second random delay circuit configured to delay outputting the second output based on the random delay; and a fault detection circuit configured to receive the first output and the delayed second output, and to generate a comparison result based on comparing the first input to the delayed second output.

Abstract: A semiconductor device includes: a carrier including an electronic circuit; a plurality of semiconductor chip packages mounted on the carrier, each of the chip packages including an encapsulation encapsulating the semiconductor chip, a plurality of contact structures electrically connecting the semiconductor chip with the electronic circuit, and at least one cooling structure protruding from the encapsulation; and a cooling element thermally conductively connected to at least one cooling structure of each of at least two of the plurality of semiconductor chip packages.

Abstract: A magnetic field sensor package includes a sensor housing; a first sensor chip having an integrated first differential magnetic field sensor circuit, the first sensor chip being arranged in the sensor housing; a second sensor chip having an integrated second differential magnetic field sensor circuit, the second sensor chip being arranged in the sensor housing; a common leadframe arranged in the sensor housing and interposed between the first sensor chip and the second sensor chip; and an insulating layer arranged in the sensor housing interposed between the first sensor chip and the common leadframe. The first sensor chip is coupled to the common leadframe via the insulating layer. Additionally, the insulating layer electrically insulates the first sensor chip from the common leadframe such that the first sensor chip and the second sensor chip are galvanically decoupled from each other.

Abstract: A radio frequency (RF) system includes a radar monolithic microwave integrated circuit (MMIC), which includes: a phase detector including a test input port, and a monitoring input port, wherein the phase detector is configured to generate an output signal that represents a phase difference between a test signal received at the test input port and a monitoring signal received at the monitoring input port; a test signal path including at least one active component, the test signal path configured to receive a local oscillator signal and provide the local oscillator signal as the test signal to the test input port during a first measurement interval; and a passive signal path configured to receive the local oscillator signal and provide the local oscillator signal to the monitoring input port as the monitoring signal during the first measurement interval.

Abstract: A radio frequency switch device includes a first transistor and a second transistor; a compensation network coupled between a body terminal of the first transistor and a source/drain terminal of the second transistor; and a bootstrapping network having a first terminal coupled to a first bias terminal, a second terminal coupled to a gate terminal of the first transistor, and a third terminal coupled to the body terminal of the first transistor, wherein the bootstrapping network establishes a low impedance path between the gate terminal and the body terminal of the first transistor in response to a first voltage value of the first bias terminal, and wherein the bootstrapping network establishes a high impedance path between the gate terminal and the body terminal of the first transistor in response to a second voltage value of the first bias terminal.

Abstract: A method for determining a reflectivity value indicating a reflectivity of an object is provided. The method includes performing a Time-of-Flight (ToF) measurement using a ToF sensor. A correlation function of the ToF measurement increases over distance within a measurement range of the ToF sensor such that an output value of the ToF sensor for the ToF measurement is independent of the distance between the ToF sensor and the object. The method further includes determining the reflectivity value based on the output value of the ToF sensor for the ToF measurement.

Abstract: A microfabricated structure includes a perforated stator; a first isolation layer on a first surface of the perforated stator; a second isolation layer on a second surface of the perforated stator; a first membrane on the first isolation layer; a second membrane on the second isolation layer; and a pillar coupled between the first membrane and the second membrane, wherein the first isolation layer includes a first tapered edge portion having a common surface with the first membrane, wherein the second isolation layer includes a first tapered edge portion having a common surface with the second membrane, and wherein an endpoint of the first tapered edge portion of the first isolation layer is laterally offset with respect to an endpoint of the first tapered edge portion of the second isolation layer.

Abstract: A method for fabricating a semiconductor device includes providing a semiconductor die, arranging an electrical connector over the semiconductor die, the electrical connector including a conductive core, an absorbing feature arranged on a first side of the conductive core, and a solder layer arranged on a second side of the conductive core, opposite the first side and facing the semiconductor die, and soldering the electrical connector onto the semiconductor die by heating the solder layer with a laser, wherein the laser irradiates the absorbing feature and absorbed energy is transferred from the absorbing feature through the conductive core to the solder layer.

Abstract: A MEMS device includes a package for providing an inner volume, a MEMS microphone arranged in the inner volume, a sound port through the package to the inner volume, and a passive acoustic attenuation filter acoustically coupled to the sound port.

Abstract: An apparatus includes a semiconductor-based substrate with a functional structure that is formed in or on the semiconductor-based substrate. The apparatus includes a frame structure surrounding the functional structure and includes a coating that covers the functional structure and is delimited by the frame structure.

Abstract: A Signal Processing Unit (SPU) having a thresholding circuit configured to detect a peak cell of a radar data cube, and to output an identification of the peak cell and energy values of the peak cell and its adjacent cells; and an interpolation circuit coupled to the thresholding circuit, and configured to determine and transmit from the SPU to a Digital Signal Processor (DSP), a relative position of the peak cell between the adjacent cells based on the energy values.

Abstract: A molded semiconductor package includes: a semiconductor die; a substrate attached to a first side of the semiconductor die; a plurality of leads electrically connected to a pad at a second side of the semiconductor die opposite the first side; a heat sink clip thermally coupled to the pad; and a molding compound encapsulating the semiconductor die, part of the leads, part of the heat sink clip, and at least part of the substrate. The molding compound has a first main side, a second main side opposite the first main side and at which the substrate is disposed, and an edge extending between the first main side and the second main side. The leads protrude from opposing first and second faces of the edge of the molding compound. The heat sink clip protrudes from opposing third and fourth faces of the edge of the molding compound.

Abstract: A digital phase-locked loop (DPLL) circuit includes: a first time-to-digital converter (TDC) and a first digital loop filter (DLF) that are configured to be coupled between a reference clock source and a digitally controlled oscillator (DCO), where the first TDC is configured to, during an acquisition mode, generate a phase error by: receiving a reference clock signal from the reference clock source; receiving a clock signal that is based on an output of the DCO divided by a dividing factor, computing a phase error using the reference clock signal and the clock signal; detecting cycle slipping in the computed phase error; and in response to detecting the cycle slipping, modifying the computed phase error to reduce the impact of cycle slipping on the DPLL circuit; and a first frequency divider circuit configured to generate the clock signal by dividing the output of the DCO by the dividing factor.

Abstract: Signal processing circuitry includes at least one processor configured to obtain a digitized radar signal, and further configured, for one or more iterations, to: determine a first power of at least one first signal sample of the radar signal; determine a second power of at least one second signal sample of the radar signal, the at least one second signal sample being subsequent in time to the at least one first signal sample; and determine a difference value between the second power and the first power. The at least one processor further configured to detecting a burst interference signal occurring within the radar signal based on the one or more difference values from the one or more iterations.

Abstract: The present disclosure relates to a hybrid multiple-input multiple-output (MIMO) radar concept. Via a first subset of a plurality of transmit channels and during a first time interval, first frequency-modulated continuous-wave (FMCW) radar signals are con-currently transmitted with different phase offsets among different transmit channels of the first subset in accordance with a first predefined code division multiplexing scheme. Via a second subset of the transmit channels and during a second time interval subsequent to the first time interval, second FMCW radar signals are concurrently transmitted with different phase offsets among different transmit channels of the second subset in accordance with a second predefined code division multiplexing scheme.

Abstract: A data storage device comprises a plurality of storage elements, each storage element configured for storing a piece of information. The plurality of storage elements is accessible as a plurality of word sets, each word set comprising a set of storage elements, and is accessible as a plurality of slice sets, each slice set comprising a set of storage elements. Each storage element is a part of a word set and a part of a slice set. The device further comprises a control unit configured for obtaining word information and slice information and for executing a write operation to parallelly write the word information into a first word set of the plurality of word sets and the slice information into a first slice set of the plurality of slice sets, wherein the first word set and the first slice set comprise a common storage element defined by an overlap of the first word set and the first slice set in a layout of the plurality of storage elements.