Abstract: A redundancy system includes a first computational device and a second computational device each configured to receive at least one input and to generate a first output and a second output, respectively, based on the at least one input; a random sequence generator configured to generate a random bit sequence; a random delay selector configured to determine a random delay based on the random bit sequence; a first random delay circuit configured to delay outputting the at least one input to the first computational device based on the random delay; a second random delay circuit configured to delay outputting the second output based on the random delay; and a fault detection circuit configured to receive the first output and the delayed second output, and to generate a comparison result based on comparing the first input to the delayed second output.

Abstract: A method for determining a reflectivity value indicating a reflectivity of an object is provided. The method includes performing a Time-of-Flight (ToF) measurement using a ToF sensor. A correlation function of the ToF measurement increases over distance within a measurement range of the ToF sensor such that an output value of the ToF sensor for the ToF measurement is independent of the distance between the ToF sensor and the object. The method further includes determining the reflectivity value based on the output value of the ToF sensor for the ToF measurement.

Abstract: A microfabricated structure includes a perforated stator; a first isolation layer on a first surface of the perforated stator; a second isolation layer on a second surface of the perforated stator; a first membrane on the first isolation layer; a second membrane on the second isolation layer; and a pillar coupled between the first membrane and the second membrane, wherein the first isolation layer includes a first tapered edge portion having a common surface with the first membrane, wherein the second isolation layer includes a first tapered edge portion having a common surface with the second membrane, and wherein an endpoint of the first tapered edge portion of the first isolation layer is laterally offset with respect to an endpoint of the first tapered edge portion of the second isolation layer.

Abstract: A method for fabricating a semiconductor device includes providing a semiconductor die, arranging an electrical connector over the semiconductor die, the electrical connector including a conductive core, an absorbing feature arranged on a first side of the conductive core, and a solder layer arranged on a second side of the conductive core, opposite the first side and facing the semiconductor die, and soldering the electrical connector onto the semiconductor die by heating the solder layer with a laser, wherein the laser irradiates the absorbing feature and absorbed energy is transferred from the absorbing feature through the conductive core to the solder layer.

Abstract: A MEMS device includes a package for providing an inner volume, a MEMS microphone arranged in the inner volume, a sound port through the package to the inner volume, and a passive acoustic attenuation filter acoustically coupled to the sound port.

Abstract: An apparatus includes a semiconductor-based substrate with a functional structure that is formed in or on the semiconductor-based substrate. The apparatus includes a frame structure surrounding the functional structure and includes a coating that covers the functional structure and is delimited by the frame structure.

Abstract: A Signal Processing Unit (SPU) having a thresholding circuit configured to detect a peak cell of a radar data cube, and to output an identification of the peak cell and energy values of the peak cell and its adjacent cells; and an interpolation circuit coupled to the thresholding circuit, and configured to determine and transmit from the SPU to a Digital Signal Processor (DSP), a relative position of the peak cell between the adjacent cells based on the energy values.

Abstract: A molded semiconductor package includes: a semiconductor die; a substrate attached to a first side of the semiconductor die; a plurality of leads electrically connected to a pad at a second side of the semiconductor die opposite the first side; a heat sink clip thermally coupled to the pad; and a molding compound encapsulating the semiconductor die, part of the leads, part of the heat sink clip, and at least part of the substrate. The molding compound has a first main side, a second main side opposite the first main side and at which the substrate is disposed, and an edge extending between the first main side and the second main side. The leads protrude from opposing first and second faces of the edge of the molding compound. The heat sink clip protrudes from opposing third and fourth faces of the edge of the molding compound.

Abstract: A digital phase-locked loop (DPLL) circuit includes: a first time-to-digital converter (TDC) and a first digital loop filter (DLF) that are configured to be coupled between a reference clock source and a digitally controlled oscillator (DCO), where the first TDC is configured to, during an acquisition mode, generate a phase error by: receiving a reference clock signal from the reference clock source; receiving a clock signal that is based on an output of the DCO divided by a dividing factor, computing a phase error using the reference clock signal and the clock signal; detecting cycle slipping in the computed phase error; and in response to detecting the cycle slipping, modifying the computed phase error to reduce the impact of cycle slipping on the DPLL circuit; and a first frequency divider circuit configured to generate the clock signal by dividing the output of the DCO by the dividing factor.

Abstract: Signal processing circuitry includes at least one processor configured to obtain a digitized radar signal, and further configured, for one or more iterations, to: determine a first power of at least one first signal sample of the radar signal; determine a second power of at least one second signal sample of the radar signal, the at least one second signal sample being subsequent in time to the at least one first signal sample; and determine a difference value between the second power and the first power. The at least one processor further configured to detecting a burst interference signal occurring within the radar signal based on the one or more difference values from the one or more iterations.

Abstract: The present disclosure relates to a hybrid multiple-input multiple-output (MIMO) radar concept. Via a first subset of a plurality of transmit channels and during a first time interval, first frequency-modulated continuous-wave (FMCW) radar signals are con-currently transmitted with different phase offsets among different transmit channels of the first subset in accordance with a first predefined code division multiplexing scheme. Via a second subset of the transmit channels and during a second time interval subsequent to the first time interval, second FMCW radar signals are concurrently transmitted with different phase offsets among different transmit channels of the second subset in accordance with a second predefined code division multiplexing scheme.

Abstract: A data storage device comprises a plurality of storage elements, each storage element configured for storing a piece of information. The plurality of storage elements is accessible as a plurality of word sets, each word set comprising a set of storage elements, and is accessible as a plurality of slice sets, each slice set comprising a set of storage elements. Each storage element is a part of a word set and a part of a slice set. The device further comprises a control unit configured for obtaining word information and slice information and for executing a write operation to parallelly write the word information into a first word set of the plurality of word sets and the slice information into a first slice set of the plurality of slice sets, wherein the first word set and the first slice set comprise a common storage element defined by an overlap of the first word set and the first slice set in a layout of the plurality of storage elements.

Abstract: A memory device comprises a plurality of memory cells and a plurality of evaluation elements, wherein each evaluation element of the plurality of evaluation elements is connectable with a memory cell of the memory device. The memory device further comprises an interconnection unit configured for connecting the plurality of memory cells to a first assignment of evaluation elements in a first state and for connecting the same plurality of memory cells to a second assignment of the evaluation elements in a second state. The memory device comprises an evaluation unit configured for controlling the interconnection unit to transition from the first state to the second state. The evaluation unit is configured for evaluating the plurality of memory cells in the first state to obtain a first evaluation result, and for evaluating the plurality of memory cells in the second state to obtain a second evaluation result.

Abstract: In accordance with an embodiment, a circuit includes: a pass transistor drive circuit including an digital input, and at least one output configured to be coupled to at least one pass transistor; a digital feedback circuit having a first analog input configured to be coupled to the at least one pass transistor, and a digital output coupled to the digital input of the pass transistor drive circuit; and an analog feedback circuit including a second analog input configured to be coupled to the at least one pass transistor, and an analog output coupled to an over voltage node of the pass transistor drive circuit, where the analog feedback circuit has a DC gain greater than zero.

Abstract: In an example, a substrate is oriented to a target axis, wherein a residual angular misalignment between the target axis and a preselected crystal channel direction in the substrate is within an angular tolerance interval. Dopant ions are implanted into the substrate using an ion beam that propagates along an ion beam axis. The dopant ions are implanted at implant angles between the ion beam axis and the target axis. The implant angles are within an implant angle range. A channel acceptance width is effective for the preselected crystal channel direction. The implant angle range is greater than 80% of a sum of the channel acceptance width and twofold the angular tolerance interval. The implant angle range is smaller than 500% of the sum of the channel acceptance width and twofold the angular tolerance interval.

Abstract: A package is disclosed. In one example, the package comprises a carrier comprising a thermally conductive and electrically insulating layer, a laminate comprising a plurality of connected laminate layers, an electronic component mounted between the carrier and the laminate. An encapsulant is at least partially arranged between the carrier and the laminate and encapsulating at least part of the electronic component.

Abstract: A radar device may include a radar transmitter to output a radio frequency (RF) transmission signal including a plurality of frequency-modulated chirps. The radar device may include a radar receiver to receive an RF radar signal, and generate, based on the RF radar signal, a dataset including a set of digital values, the dataset being associated with a chirp or a sequence of successive chirps. The radar device may include a neural network to filter the dataset to reduce an interfering signal included in the dataset, the neural network being a convolutional neural network. At least one layer of the neural network may be a complex-valued neural network layer includes complex-valued weighting factor, where the complex-valued neural network layer is configured to perform one or more operations according to a complex-valued computation.

Abstract: A method is described. The method comprises determining a first measurement signal (CS1) which depends on a first load current (I1) through a first transistor (Q1) which is connected in series to a load (Z); determining a second measurement signal (CS2) which depends on a second load current (I2) through a second transistor (Q2) which is connected in series to the load (Z); and comparing the first measurement signal (CS1) and the second measurement signal (CS2), in order to detect the presence of an error.

Abstract: A method includes exposing gas sensitive material of a gas sensor device to different adjusted target gas concentrations, determining measurement values of the resistance of the gas sensitive material between first and second contact regions in response to the adjusted target gas concentration, determining a first gas sensor behavior model based on the measurement values of the resistance of the gas sensitive material as a function of the adjusted target gas concentration, translating the first gas sensor behavior model into a corresponding second gas sensor behavior model for the resistance of the gas sensitive material as a function of a control voltage, and sweeping the control voltage based on the second gas sensor behavior model over a control voltage range for providing control voltage dependent resistance data, wherein the control voltage dependent resistance data over the control voltage range form the calibration data for the gas sensor device.

Abstract: A method of calibrating an analog front end (AFE) filter of a radio frequency integrated circuit (RFIC) includes: making a first measurement of the RFIC at a first measuring frequency while the AFE filter is bypassed; generating a first amplitude estimate and a first phase estimate at the first measuring frequency using the first measurement; making a second measurement of the RFIC at the first measuring frequency while the AFE filter is turned on; generating a second amplitude estimate and a second phase estimate at the first measuring frequency using the second measurement; and calculating a frequency response of the AFE filter at the first measuring frequency, which includes calculating an amplitude response of the AFE filter based on the second amplitude estimate and the first amplitude estimate; and calculating a phase response of the filter based on the first phase estimate and the second phase estimate.