Abstract: A process and intermediate DRAM structure formed by providing a substrate having an array of trenches containing trench capacitors underlying vertical transistors in an array area separated by isolation trenches residing in both array and support areas. A top oxide nitride (TON) liner is deposited over array and support areas so as to directly contact the fill in the isolation trenches. An array top oxide (ATO) is then deposited directly over the TON liner such that during subsequent processing, the TON protects the isolation trench oxide from any divot opening etches while maintaining the isolation trench oxide height fixed during the ATO process. In further processing the intermediate structure, ATO and TON are removed from the support area only, leaving remaining portions of both ATO and TON only in the array area, such that the TON liner separates the ATO from the isolation trench fill.

Abstract: A material layer on a substrate being processed, e.g. to form chips, includes one or more functional structures. In order to control pattern density during fabrication of the chip, dummy fill structures of different sizes and shapes are added to the chip at different distances from the functional structures of the material layer. In particular, the placement, size and shape of the dummy structures are determined as a function of a distance to, and density of, the functional structures of the material layer.

Abstract: A system, an automatic machine-implemented method, and a machine-readable medium recording a set of instructions to perform such method are provided for de-compacting a layout for a portion of an integrated circuit. According to the method, a spacing is enlarged between neighboring features of a path of a plurality of paths of the layout provided that the length of the path does not then exceed a predetermined dimensional constraint and connectivity is maintained between the neighboring features and any features of the layout to which they are connected. This process is repeated to enlarge at least one other spacing of the layout.

Abstract: A method for monitoring a nitridation process, including: (a) providing a semiconductor substrate; (b) forming a first dielectric layer on a top surface of the substrate; (c) introducing a quantity of interfacial species into the substrate; (d) removing the first dielectric layer; (e) forming a second dielectric layer on the top surface of the substrate; (f) measuring the density of interface traps between the substrate and the second dielectric layer; (g) providing a predetermined relationship between the quantity of the interfacial species and the density of the interface traps; and (h) determining the quantity of the interfacial species introduced based on the relationship.

Abstract: A system and method are provided for reducing a rate for refreshing a portion of a dynamic random access memory (DRAM). The method includes storing a information for distinguishing between a first portion of a DRAM requiring refresh at a first rate and a second portion of said DRAM permitting refresh at a second rate lower than the first rate. The stored information is then accessed to refresh the first portion of the DRAM at the first rate and to refresh the second portion at the second rate. The information can be generated from post-fabrication stress testing such that most of the DRAM can be refreshed at the lower rate and only the portion requiring more frequent refresh is refreshed at the higher rate.

Abstract: A wafer having a top surface including a first material such as silicon dioxide or silicon nitride and a second material such as polysilicon or copper is etched so as to leave elements formed from the second material projecting above the surrounding surface defined by the first material. An opaque layer may be applied over the newly-formed top surface covered by a transparent layer such as a photoresist. The opaque layer has raised features corresponding to the projecting features formed from the second material. These raised features provide contrast and allow an optical system to locate the wafer as, for example, in registering the wafer in a wafer stepper. Alternatively, transparent layers such as an oxide dielectric and a photoresist may be applied after etching. The projecting elements formed by etching remain visible through the transparent layers and similarly allow optical location.

Abstract: In vertical transistor trench DRAM arrays, the problem of pinching off the transistor bodies in the P-well is addressed by etching a set of trenches between the DRAM cell trenches down to a level below the buried straps, thus blocking the depletion regions from the buried straps from meeting. The trench structure contains conductive material that forms a conductive path from the bodies of the vertical transistors to the lower portion of the P-well.

Abstract: Information concerning a condition of a fuse is stored in a latch circuit and may be corrected. A first signal is supplied to the latch circuit which sets the latch circuit in a first state when the fuse is in a first condition and keeps the latch circuit unchanged when the fuse is in a second condition. While the first signal is being supplied, a second signal is supplied to the latch circuit that keeps the latch circuit in the first state when the fuse is in the first condition and sets the latch circuit in a second state when the fuse is in the second condition.

Abstract: The present invention a system and method are provided for performing an inter-frequency search with reduced loss of link frames in a CDMA system. The CDMA system includes a base station (20) and a mobile station (50). The mobile station (50) has a searcher (164), which searches for pilot channels. The signal strengths of these pilot channels are then reported to the base station (20). This searching results in erased portions of a data frame (238). After the signal strengths are reported to the base station (20), the mobile station (50) informs the base station (20) of the parameters related to the search. These parameters may include the frame of the search, the start position of the search, and the length of the search. The mobile station (50) and the base station (20) then replaces the erased portions of the frame with corrective data such as soft zeros.

Abstract: A method is provided for correcting rule violating areas of a photomask using a digital representation of the photomask. The method includes identifying violating areas of the photomask from a digital representation of the photomask. The violating areas include areas that violate a minimum width rule and/or areas that violate a minimum space rule for the photomask. The violating areas are then manipulated for the purpose of eliminating the violating areas. They are manipulated differently based on whether the violating area lies inside a design shape of a layout pattern to be imaged using the photomask and/or whether the violating area lies outside the design shape.

Abstract: A system and method for acquisition signal error estimation is provided which uses one or more past values of the sequence to determine the nearest ideal sample value without comparing the received sample value to the potential sample values. According to one embodiment, the nearest ideal sample value is selected based on the received sample value and values of three consecutive samples. According to another embodiment, the nearest ideal sample value is selected based on the received sample value and a value of an immediately preceding sample. According yet to another embodiment, the nearest ideal sample value is selected based on the received sample value and a value of a previous sample. The acquisition signal error estimator maybe used in conjunction with gain, DC offset, or magneto-resistive asymmetry control loops in a sampled amplitude read channel.

Abstract: A device structure and method for forming an interconnect structure in a magnetic random access memory (MRAM) device. In an exemplary embodiment, the method includes defining a magnetic stack layer on a lower metallization level, the magnetic stack layer including a non-ferromagnetic layer disposed between a pair of ferromagnetic layers. A conductive hardmask is defined over the magnetic stack layer, and selected portions of the hardmask and the magnetic stack layer, are then removed, thereby creating an array of magnetic tunnel junction (MTJ) stacks. The MTJ stacks include remaining portions of the magnetic stack layer and the hardmask, wherein the hardmask forms a self aligning contact between the magnetic stack layer and an upper metallization level subsequently formed above the MTJ stacks.

Abstract: A system and method is provided for controlling the impedance and current of an off chip driver circuit to match to load driven by the driver and for reducing noise and ringing in the off chip driver circuit. The driver comprises a pull up transistor for switching the output of the driver to a high-voltage, a pull down transistor for switching the output of the driver to a low voltage, a first current mirror transistor coupled to the pull up transistor for controlling the current transmitted to a load connected to the driver when the output of the driver is at the high-voltage, and a second current mirror transistor coupled to the pull down transistor for controlling the current transmitted to the load when the output of the driver is at the low voltage. In addition, the driver may include a first pre-driver providing a gate signal for the pull up transistor having a controlled slew rate and a second pre-driver providing a gate signal for the pull down transistor having a controlled slew rate.

Abstract: As disclosed herein, a method and apparatus are provided for amplifying a signal by a transistor of an array of transistors that includes a storage cell transistor array of a dynamic random access memory (DRAM). According to the disclosed method, an array of transistors is provided including transistors of a storage cell transistor array of a dynamic random access memory array. A transistor of the array of transistors has a source or a drain coupled to a fixed potential. An input signal is applied to a gate of the transistor, whereby the transistor amplifies the input signal to provide an output signal appearing on the other of the source or drain of the transistor.

Abstract: A semiconductor device is fabricated to have improved bitline contact formation. Polysilicon is deposited between gate contacts that connect to transistors of DRAM memory cells. The polysilicon covers the gate contacts and continues to cover the gate contacts during subsequent processing steps. A bitline of, e.g., tungsten, is deposited so that it contacts at least a portion of the polysilicon, thereby providing electrical contact with the DRAM transistors.

Abstract: An integrated circuit, comprising: at least one main circuit operable to perform one or more functions, and including at least one I/O node for receiving or transmitting an operating signal; an active termination circuit having first and second MOSFETs of the same type coupled in series across a Vdd node of a first source potential and a Vss node of a second source potential, the at least one I/O node being coupled to a common node between the first and second MOSFETs; and a control circuit operable to bias the first and second MOSFETs such that they exhibit a controlled impedance at the common node.

Abstract: Devices formed in a substrate are protected from shining spots present in a periphery of the substrate. A ring of material is formed on the substrate to separate the periphery of the substrate from a further region of the substrate where the devices are formed.

Abstract: A semiconductive wafer having a layer of conductive material formed thereon is polished. The semiconductor wafer is rotated against an abrasive polishing pad. A solution is applied to the semiconductor wafer and to the abrasive polishing pad. The solution includes an etchant of the conductive material.

Abstract: An integrated circuit memory is provided in which a multiplexer is operable to select one of a plurality of bitlines to couple to a master bitline using select transistors of an array of transistors, the array of transistors including access transistors of a storage cell array of the memory.

Abstract: There is provided a method for measuring planarized features on a wafer of a semiconductor device. The planarized features on the wafer are illuminated. A reflected light beam with respect to the planarized features is detected. Optical characteristics of the reflected light beam are analyzed to determine information corresponding to the planarized features. Preferably, the analyzing step maximizes an analysis of the optical characteristics based upon a simplified geometry of the planarized features with respect to a geometry of similar, un-planarized features. Moreover, preferably, the analyzing step maximizes an analysis of the optical characteristics based upon a reduction in complexity of the planarized features due to a similarity in refractive indexes corresponding to a bulk silicon substrate and a poly silicon fill of the semiconductor device.