Abstract: A reduction in the intersection of vias on the last layer (“VL”) and holes in the last thin metal layer (“MLHOLE”) can be achieved without degrading product yield or robustness or increasing copper dishing. The mutation of some dense redundant VLs to MLHOLEs decreases the number of intersections between VLs and MLHOLEs.

Abstract: An integrated circuit chip including a first delay circuit and a second delay circuit. The first delay circuit has a first delay circuit topology configured to delay a signal a first delay. The second delay circuit has a second delay circuit topology configured to provide a second delay in a circuit loop that is configured to be monitored and provide an oscillating signal. The second delay circuit topology is substantially the same as the first delay circuit topology and the first delay circuit is configured to be trimmed to adjust the first delay based on the second delay and the oscillating signal.

Abstract: According to one embodiment a network switch is disclosed. The switch includes a first media access controller (MAC) coupled to a plurality of ports and a memory controller coupled to the first MAC. The memory controller is adaptable to write a first portion of packet data received from a first of the plurality of ports to a first memory device and write a second portion of the packet data from the first port to a second memory device.

Abstract: An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.

Abstract: A dynamic random access memory device is capable of converting from a full density memory device to a reduced density memory device. The reduced density memory device compensates for cell failures in a plurality of cell blocks, regardless of the location of the cell failures. The memory device includes a row address mapping fuse for selectively determining row address combinations capable of storing data bits. A row address mapping logic is coupled to the row address mapping fuse and is capable of routing data bits to the address combinations capable of storing data bits.

Abstract: An apparatus for processing packets in a multimedia terminal has a media access controller to send and receive packets from a network. A digital signal processor converts a series of incoming real-time transfer protocol packets into an incoming digital signal and converts an outgoing digital signal into a series of outgoing real-time transfer protocol packets. A compression-decompression unit decompresses the incoming digital signal and generates an output signal to an output device and compresses an input signal from an input device and generates an outgoing digital signal. A central processing unit sends and receives transmission control protocol packets. The apparatus can store a packet in one of a plurality of queues in a buffer and assign a priority to the packet based on whether the packet is a real-time transfer protocol packet or a transfer control protocol packet.

Abstract: A method and system of controlling out of order execution pipelines using pipeline skew parameters is disclosed. The pipeline skew parameters track the relative position of a load/store instruction in a load/store pipeline and a simultaneously issued integer instruction in a variable length integer pipeline. The pipeline skew parameters are used to improve data hazard detection, pipeline stalling, and instruction cancellation.

Abstract: The present invention relates to a coding system characterized by various combinations of the following properties: 1) Even parity at the output of d of the precoder; 2) A coding rate of 32/34; 3) At least 9 ones per codeword; 4) No more than 13 consecutive zeros in the stream of encoded data (G=13); 5) No more than 13 consecutive zeros in any run of every-other-bit in the stream of codewords (I=13); 6) For closed error events in y or y? having squared-distance?(1 to 1.5)×dmfb2 in the detector, the decoder produces at most 4 corresponding erroneous data bytes; 7) Decoding of a 34 bit codeword may begin when 19 of its bits have been received; 8) If the Viterbi detector 108 outputs Non-Return to Zero (NRZ) symbols, then its output is filtered by (1?D^2) before being decoded, but if the Viterbi detector outputs NRZ Inverter (NRZI) symbols, then its output is decoded directly; and 9) The even parity is on NRZ symbols.

Abstract: A phase shift mask shape that reduces line-end shortening at the critical feature without changing layout size increases required of requisite phase shift rules. The phase feature is given an angled extension, which includes the lithographic shortening value. This allows the critical shape to be designed much closer to the reference layer then it could without the angled extension feature. Phase mask extension features beyond a given device segment are significantly reduced by lengthening the feature along an uncritical portion; moving the feature reference point to the device layer; and flattening the phase extension feature into an L-shape or T-shape along the uncritical parts of a device segment. Applying these design rules allows a draw of the gate conductor under current conditions and puts phase shapes inside without extending the gate conductor dimensions to the next feature.

Abstract: A method and system for routing a multicast packet through a unicast packet switch network of devices. A virtual destination group, which includes destination devices of the multicast packet, is defined, and then the virtual destination group is mapped to an unused unicast destination encoding in routing tables of the devices. The multicast packet is then routed from a source device to the destination devices using the routing tables.

Abstract: A testing system or method compares read data from one or more dies in a semiconductor wafer with the original data written onto the one or more dies The testing system includes one or more write registers connected to one or more dies on the semiconductor wafer. One or more comparators are connected to the dies and the write registers. The comparator generates a result in response to the original data and the read data.

Abstract: A bi-directional isolation scheme is described in which digital data, including clock information, may be communicated bi-directionally across a single isolation barrier without requiring a phase locked loop (PLL) based clock recovery procedure. In this way, the lead-time needed by the receiving circuit to recover the data clock signal may be reduced and the polarity (or 180° phase) ambiguities often associated with PLL-based methods may be avoided.

Abstract: A process and intermediate DRAM structure formed by providing a substrate having an array of trenches containing trench capacitors underlying vertical transistors in an array area separated by isolation trenches residing in both array and support areas. A top oxide nitride (TON) liner is deposited over array and support areas so as to directly contact the fill in the isolation trenches. An array top oxide (ATO) is then deposited directly over the TON liner such that during subsequent processing, the TON protects the isolation trench oxide from any divot opening etches while maintaining the isolation trench oxide height fixed during the ATO process. In further processing the intermediate structure, ATO and TON are removed from the support area only, leaving remaining portions of both ATO and TON only in the array area, such that the TON liner separates the ATO from the isolation trench fill.

Abstract: A memory comprises a column decoder and a circuit. The circuit is configured to receive a column address strobe signal, a column active signal, and a column addresses signal. The circuit is configured to pass the column addresses signal to the column decoder if the column address strobe signal and the column active signal are at a first logic level, and latch the column addresses signal and pass the latched column addresses signal to the column decoder if one of the column address strobe signal and the column active signal are at a second logic level different from the first logic level.

Abstract: The present invention provides techniques for data storage. In one aspect of the invention, a semiconductor device is provided. The semiconductor device comprises at least one free layer and at least one fixed layer, with at least one barrier layer therebetween. At least one pinned magnetic layer is separated from the at least one free layer by at least one non-magnetic layer, the at least one pinned magnetic layer and non-magnetic layer being configured to cancel out at least a portion of a Neel coupling between the at least one free layer and the at least one fixed layer.

Abstract: A calibrated magnetic random access memory (MRAM) current sense amplifier includes a first plurality of trim transistors selectively configured in parallel with a first load device, the first load device associated with a data side of the sense amplifier. A second plurality of trim transistors is selectively configured in parallel with a second load device, the second load device associated with a reference side of the sense amplifier. The first and said second plurality of trim transistors are individually activated so as to compensate for device mismatch with respect to the data and reference sides of the sense amplifier.

Abstract: A network processor (12) for a voice over Internet protocol phone integrates a universal serial bus port (56), a pair of IEEE 802.3 MACs (70a), a repeater (70b), and a pair of pulse code modulation (PCM) ports (24) such that the network processor can be combined with other peripherals to transmit both voice and data over an Internet protocol network (13).

Abstract: Techniques for processing magnetic devices are provided. In one aspect, a method of processing a magnetic device including two or more anti-parallel coupled layers comprises the following steps. A magnetic field is applied in a given direction to orient a direction of magnetization of the two or more anti-parallel coupled layers. The direction of the applied magnetic field is rotated in relation to a positioning of the two or more anti-parallel coupled layers to counteract at least a portion of a change in a direction of magnetization experienced by at least one of the two or more anti-parallel coupled layers when the applied magnetic field is reduced.

Abstract: A random access memory includes a first circuit configured to receive a strobe signal and provide pulses in response to transitions in the strobe signal, and a second circuit configured to receive the strobe signal to latch data into the second circuit in response to the strobe signal, and to receive the pulses to re-latch the latched data into the second circuit after the transitions in the strobe signal. The first circuit includes an enable circuit configured to provide an enable signal and a buffer circuit configured to receive the strobe signal and the enable signal and provide the pulses in response to the enable signal and the strobe signal. The enable circuit is configured to receive the pulses from the buffer circuit and stop providing the enable signal to the buffer circuit in response to receiving the pulses.

Abstract: A random access memory with a low power mode indicator. The random access memory includes a state machine for generating a power mode output signal. A power mode pin control circuit is connected to the state machine for receiving the power mode output signal. A power mode pin is connected to the power mode pin control circuit for providing an output indicative of the power mode output signal received from the state machine.