Abstract: Methods and devices that provide improved isolation and alignment of gate conductors or gate contacts of vertical transistors in deep trench memory cells. A method for forming a vertical gate contact of a vertical transistor includes an oxide spacer formation process that prevents defects, such as shorts caused by voids filled with polysilicon, resulting from etching processes that are performed during fabrication of a vertical transistor, and enables formation of well-defined contact plugs for gate contacts, providing improved alignment structures.

Abstract: A 1000BASE-T transceiver linked to an unshielded twisted pair (UTP) through a transformer currently transmits and receives outgoing and incoming signals via the UTP. The transceiver employs an energy efficient class B or AB line driver supplying asymmetric output currents to the transformer's primary winding terminals so that the transformer's secondary winding induces the outgoing signal on the UTP. Resistors couple the transformer's primary winding terminals to inputs of separate amplifiers producing a differential output signal mimicking the incoming 1000BASE-T signal. Since both the incoming and outgoing signals contribute to voltages appearing at the transformer's primary winding terminals, echo cancellation circuits provide additional compensating signals to the amplifier inputs for canceling echo in each amplifier input due to the resistive and reactive loading on each driver output current and arising from the asymmetric nature of the class B or AB driver's output currents.

Abstract: A semiconductor transistor structure includes a substrate having an epitaxial layer, a source region extending from the surface of the epitaxial layer, a drain region within the epitaxial layer, a channel located between the drain and source regions, and a gate arranged above the channel. The drain region includes a first region for establishing a contact with an electrode, a second region being less doped than the first region being buried within the epitaxial layer and extending from the first region horizontally in direction towards the gate, a third region less doped than the second region and extending vertically from the surface of the epitaxial layer and horizontally from the second region until under the gate, a top layer extending from the surface of the epitaxial layer to the second region, and a bottom layer extending from the second region into the epitaxial layer.

Abstract: The present invention provides techniques for data storage. In one aspect of the invention, a semiconductor device is provided. The semiconductor device comprises at least one free layer and at least one fixed layer, with at least one barrier layer therebetween. At least one pinned magnetic layer is separated from the at least one free layer by at least one non-magnetic layer, the at least one pinned magnetic layer and non-magnetic layer being configured to cancel out at least a portion of a Neel coupling between the at least one free layer and the at least one fixed layer.

Abstract: A method and apparatus for providing a plurality of aligned instructions from an instruction stream provided by a memory unit for execution within a pipelined microprocessor is described. The microprocessor comprises a prefetch buffer, whereby the prefetch buffer stores prefetched instructions and additional information about the validity and size of the prefetch buffer. The method and apparatus use the prefetch buffer to buffer a part of an instruction stream. The actually aligned instruction stream is issued from the prefetch buffer or directly by instructions fetched from the memory, or from a combination of prefetched instructions and actually fetched instructions.

Abstract: A method of patterning a magnetic tunnel junction (MTJ) stack is provided. According to such method, an MTJ stack is formed having a free layer, a pinned layer and a tunnel barrier layer disposed between the free layer and the pinned layer. A first area of the MTJ stack is masked while the free layer of the MTJ is exposed in a second area. The free layer is then rendered electrically and magnetically inactive in the second area.

Abstract: A process and intermediate DRAM structure formed by providing a substrate having an array of trenches containing trench capacitors underlying vertical transistors in an array area separated by isolation trenches residing in both array and support areas. A top oxide nitride (TON) liner is deposited over array and support areas so as to directly contact the fill in the isolation trenches. An array top oxide (ATO) is then deposited directly over the TON liner such that during subsequent processing, the TON protects the isolation trench oxide from any divot opening etches while maintaining the isolation trench oxide height fixed during the ATO process. In further processing the intermediate structure, ATO and TON are removed from the support area only, leaving remaining portions of both ATO and TON only in the array area, such that the TON liner separates the ATO from the isolation trench fill.

Abstract: An active area pattern is formed atop a deep trench pattern with a single exposure using an alternative phase-shift mask. To prevent adjacent spaces of opposite phase from intersecting one another at the ends of substantially opaque features of the active area pattern, one or more connectors are used to connect the ends of the substantially opaque patterns. Trench regions of the deep trench pattern are arranged such that the conduction path of the connectors are interrupted and prevent the lines from shorting to one another. Alternatively, a bit line pattern or a word line pattern having a lines and spaces array and a support region are printed with a single exposure using an alternating phase-shift mask. At one end of the array region, lines having a respective phase shift extend into the support region, and lines of the opposite phase shift are terminated.

Abstract: A a magnetic random access memory (MRAM) device includes a cap layer formed over a magnetic tunnel junction (MTJ) stack layer, an etch stop layer formed over the first cap layer, and a hardmask layer formed over the etch stop layer. The etch stop layer is selected from a material such that an etch chemistry used for removing the hardmask layer has selectivity against etching the etch stop layer material.

Abstract: A bi-directional isolation scheme is described in which digital data, including clock information, may be communicated bi-directionally across a single isolation barrier without requiring a phase locked loop (PLL) based clock recovery procedure. In this way, the lead-time needed by the receiving circuit to recover the data clock signal may be reduced and the polarity (or 180° phase) ambiguities often associated with PLL-based methods may be avoided.

Abstract: The present invention relates to a data processing unit for executing instructions stored in a memory comprising a plurality of registers coupled with an execution unit comprising a logic unit for execution of logic operations. The logic unit comprises a first logic operator which can be coupled with a first and second register as an input register and which generates an output bit as a result of a logic operation. It further comprises a Boolean operator which receives the output bit of the first logic operator as a first input and second input bit from a third register which generates an output bit as a result of a Boolean operation.

Abstract: A random access memory comprises a plurality of data pads and an array of memory cells comprising a first portion of memory cells and a second portion of memory cells. The random access memory comprises a first line configured to receive first data signals between the first portion of memory cells and the data pads and a second line configured to receive second data signals between the second portion of memory cells and the data pads. The first portion of memory cells is configured to be made inaccessible to eliminate the first data signals and a first number of the data pads and the second portion of memory cells is configured to be made inaccessible to eliminate the second data signals and a second number of the data pads.

Abstract: A semiconductor wafer comprises a semiconductor substrate, a surface alignment mark visible on the semiconductor surface and a plurality of nanostructures on the surface of the surface alignment mark having an average pitch adapted to reduce reflectivity of the surface alignment mark in a predetermined light bandwidth.

Abstract: A method is provided for forming an inside nitride spacer in a deep trench device DRAM cell. The method includes etching a stud from a semiconductor material including a first spacer positioned on the sidewalls of the deep trench, wherein two of the sidewalls are formed of isolation trench oxide. The method further includes depositing an oxide layer on the surface of the semiconductor, and depositing a second spacer in the deep trench of the semiconductor, wherein the second spacer has a positive taper relative to the isolation trench oxide.

Abstract: A method of projecting a pattern from a mask onto a substrate comprises providing an energy source, a substrate, and a mask containing a pattern of features to be projected onto the substrate, and projecting an energy beam from the energy source though the mask toward the substrate to create a projected mask pattern image. The projected mask pattern image is created by zeroth and higher orders of the energy beam. The method then includes diffracting zeroth order beams of the projected mask pattern image to an extent that prevents the zeroth order beams from reaching the substrate, while permitting higher order beams of the projected mask pattern image to reach the substrate. Preferably, the zeroth order beams of the projected mask pattern image are diffracted at an obtuse angle.

Abstract: A system and method for frame detection and generation. Each incoming clock-data stream is divided into two independent data streams: a clock path which preserves the timing of the individual cock domains and a data path which multiplexes an arbitrary number of data streams onto a parallel path. A framer array structure implements a context swap and synchronizes the data streams.

Abstract: An electronic device and method of forming said device are presented, in which the device comprises a base having a pair of elongate flanges and a channel portion defined therebetween, wherein the channel portion has a substantially planar first surface, and wherein the pair of flanges extend generally perpendicularly from the first surface. The device further comprises a ceramic circuit board having a substantially planar second surface, wherein the second surface is substantially parallel to the first surface, and wherein the second surface is operable to mate with the first surface within the channel. An adhesive layer generally resides between the first surface and the second surface, wherein the adhesive layer fixedly couples the first surface of the base to the second surface of the circuit board, wherein the pair of flanges substantially maintain the planarity of the first surface and the second surface during a thermal expansion or contraction of one or more of the base and the circuit board.

Abstract: A memory cell is formed for a memory cell array that is comprised of a plurality of the memory cells arranged in rows and columns. Deep trenches having sidewalls is formed within a semiconductor substrate. A buried plate region adjoining a deep trench is formed within the semiconductor substrate, and a dielectric film is formed along the sidewalls of the deep trench. A masking layer is patterned such that a portion of the dielectric film is covered by the masking layer and a remaining portion of the dielectric film is exposed. An upper region of the exposed portion of the dielectric film is removed such that a trench collar is formed along a middle portion of a side of the deep trench. The deep trench is partly filled with doped polysilicon. The dopants in the polysilicon diffuse through the side of the deep trench into adjoining regions of the semiconductor substrate during subsequent thermal processing steps to form a buried strap region along a side of the deep trench.

Abstract: A method of fabricating a filled trench structure, the method including: (a) forming a first set of trenches in a first region of a substrate and forming a second set of trenches in a second region of the substrate, trenches in the first set of trenches having a higher aspect ratio than the trenches in the second region; (b) depositing a fill material in the first and second set of trenches and on a top surface of the substrate, the fill material completely filling the trenches; (c) removing an upper portion of the fill material; and (d) removing, using a planarization process, all fill material from the top surface of the substrate, a top surface of the fill material in the first and second sets of trenches co-planer with the top surface of the substrate.

Abstract: Semiconductor devices having improved isolation are provided along with methods of fabricating such semiconductor devices. The improved isolation includes an encapsulated spacer formed within a gate region of a device.