Abstract: The properties of features formed in a substrate are measured. Interferometric illumination is used to illuminate regions of a substrate so that the features of interest occupy a greater proportion of the illuminated area. The signal-to-noise ratio of the measurement signal is therefore increased, and the sensitivity of the measurement is thus improved.

Abstract: The present invention related to doping of amorphous silicon and polysilicon in trench structures for semiconductor devices. A single gas phase doping step is performed after a thin layer of amorphous silicon or polysilicon is deposited in the trench. The gas phase doping occurs at elevated temperature and moderate pressure to yield a dopant concentration on the order of 1×1020 atoms/cm3.

Abstract: A test system for positioning and measuring the far-field pattern of a laser diode under test (LDUT) using a single objective lens and two relay lenses. Positioning is achieved by passing light from the LDUT through a video microscope formed by the objective lens and a first relay lens, which focuses the light onto an image plane for capture by a first camera. Far-field pattern measurement is performed by reflecting a portion of the focused light through a second relay lens, which collimates the light and directs the unfocused light onto an infinity image plane, where it is captured by a second video camera. Angular orientation is achieved using a laser collimator that reflects beam energy from a datum plane of the LDUT. The reflected beam energy forms a point image at the infinity image plane that is used to determine and/or adjust the angular orientation of the LDUT.

Abstract: A circuit to operate a semiconductor integrated circuit memory device having memory cells in a deep power down mode. The power down circuit includes a transistor switch connected between an external voltage source and the device memory cells and peripheral circuits, a generator for providing a control voltage of a first level different from the value of the external voltage, and a multiplexer that receives as one input the control voltage and as a second input the external voltage. The multiplexer has a selected output of one of the control voltage and external voltage that is applied to a control electrode of the transistor switch. When deep power down mode operation is required, the multiplexer responds to a power down control flag signal to apply the external voltage to the transistor control electrode to turn off the transistor and block application of the external voltage to the memory cells and peripheral circuits.

Abstract: A deep trench capacitor used in a trench DRAM includes a buried plate and an isolation collar. The deep trench is bottle-shaped, and the isolation collar is formed in upper portion of the wider region of the bottle-shaped trench. The buried plate surrounds the lower portion of the wider part of the bottle-shaped trench, and hemispherical grain polysilicon lines the walls of at least the lower portion of the wider part of the trench. A nitride liner layer lines the inner walls of the oxide collar and prevents diffusion of dopant through the oxide collar into the substrate when the HSG polysilicon and the doped buried plate are formed. The buried plate region is self-aligned to the isolation collar. The depth of the top of the wider part of the bottle shape and the bottom depth of the isolation collar are determined by successive resist deposition and recessing steps.

Abstract: One embodiment of the present invention provides a random access memory (RAM) including an array of memory cells arrange in a plurality of rows and columns, wherein access of each row is based on a wordline signal, and a wordline circuit. The wordline circuit includes a voltage node receiving a positive voltage from an external power source, a decoding node receiving a decoding signal having a state representative of an idle mode, and a driver circuit providing to at least one of the rows of memory cells a wordline signal based on the decoding signal and forming a current leakage path from the voltage node to a reference node when the decoding signal state indicates the idle mode.

Abstract: A data communications device that can operate in accordance with two or more protocols having different data formats and error-protection schemes. The protocol-dependent aspects of the device are handled by a peripheral portion of the device, allowing a substantially protocol-independent core portion that is insulated from protocol changes. Translation and/or adaptation mechanisms in the peripheral portion of the device allow the device to handle changes in data format and/or pipeline changes such as error protection without affecting the core portion of the device. A device and method are provided for inter-operating with both the Spatial Reuse Protocol (SRP) and the Resilient Packet Ring (RPR) architectures.

Abstract: A hardmask layer in the back end of an integrated circuit is formed from TaN having a composition of less than 50% Ta and a resistivity greater than 400 ?Ohm-cm, so that it is substantially transparent in the visible and permits visual alignment of upper and lower alignment marks through the hardmask and intervening layer(s) of ILD. A preferred method of formation of the hardmask is by sputter deposition of Ta in an ambient containing N2 and a flow rate such that (N2 flow)/(N2+carrier flow)>0.5.

Abstract: An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.

Abstract: A process and composition for cleaning debris from a stack etch/ion implanted CMOS device which includes a tungsten gate conductor. The composition includes sulfuric acid and hydrogen peroxide in a volume ratio of at least about 6:1. In the process the composition contacts the CMOS device at atmospheric pressure and a temperature of between about 70° C. and about 90° C.

Abstract: A method for testing a DDR DRAM having a test mode and an operational mode is described. The method including in the order recited: (a) placing the DDR DRAM in test mode; (b) issuing a bank activate command to select and bring up a wordline selected for write of the DDR DRAM; (c) writing with auto-precharge, a test pattern to cells of the DDR DRAM; (d) repeating steps (b) and (c) until all wordlines for write have been selected; (e) issuing a bank activate command to select and bring up a wordline selected for read of the DDR DRAM; (f) reading with auto-precharge, the stored test pattern from cells of the DDR DRAM; and (g) repeating steps (e) and (f) until all wordlines for read have been selected.

Abstract: An HDP process for high aspect ratio gap filling comprises contacting a semiconductor substrate with an oxide precursor under high density plasma conditions at a first pressure less than about 10 millitorr, wherein said gaps are partially filled with oxide; and further contacting the substrate with an oxide precursor under high density plasma conditions at a second pressure greater than about 10 millitorr, wherein said gaps are further filled with oxide.

Abstract: A method and structure for increasing the threshold voltage of vertical semiconductor devices. The method comprises creating a deep trench in a substrate whose semiconductor material has an orientation plane perpendicular to the surface of the substrate. Then, vertical transistors are formed around and along the depth of the deep trench. Next, two shallow trench isolation are formed such that they sandwich the deep trench in an active region and the two shallow trench isolation regions abut the active region via planes perpendicular to the orientation plane. Then, the channel regions of the vertical transistors are exposed to the atmosphere in the deep trench and then chemically etched to planes parallel to the orientation plane. Then, a gate dielectric layer is formed on the wall of the deep trench. Finally, the deep trench is filled with poly-silicon to form the gate for the vertical transistors.

Abstract: Low-k dielectric materials are incorporated as an insulator material between bit lines and an inter-level dielectric material. The device is first processed in a known manner, up to and including the deposition and anneal of the bit line metal, using a higher dielectric constant material that can withstand the higher temperature process steps as the insulator between the bit lines. Then, the higher dielectric constant material is removed using an etch that is selective to the bit line metal, and the low-k dielectric material is deposited. The low-k material may then be planarized to the top of the bit lines, and further low-k material deposited as an inter-level dielectric. Alternatively, sufficient low-k material is deposited in a single step to both fill the gaps between the bit lines as well as serve as an inter-level dielectric, and then the low-k dielectric material is planarized. Standard processing may then be carried out.

Abstract: The present invention provides a method cleaning of semiconductor devices through heterogeneous nucleation of cavitation bubbles. Heterogeneous nucleation is performed by applying sonic energy to a cleaning solution and a phase material in order to remove unwanted particles from semiconductor devices. A surfactant may be added to the phase material and the cleaning solution.

Abstract: The properties of features formed in a substrate are measured. Lenslet array illumination is used to illuminate regions of a substrate so that the features of interest occupy a greater proportion of the illuminated area. The signal-to-noise ratio of the measurement signal is therefore increased, and the sensitivity of the measurement is thus improved.

Abstract: A method for aligning an opaque, active device in a semiconductor structure includes forming an opaque layer over an optically transparent layer formed on a lower metallization level, the lower metallization level including one or more alignment marks formed therein. A portion of the opaque layer is patterned and opened corresponding to the location of the one or more alignment marks in the lower metallization level so as to render the one or more alignment marks optically visible. The opaque layer is then patterned with respect to the lower metallization level, using the optically visible one or more alignment marks.

Abstract: An isolation trench formed in a semiconductor substrate and is filled with at least one insulating liner layer that is deposited along sidewalls and a bottom region of the isolation trench and with at least one silicon liner layer that is deposited atop the insulating liner layer. An upper portion of the insulating liner layers are removed, and the silicon liner layers are removed. A remaining portion of the trench is filled with another insulating layer.

Abstract: A method of forming bitlines for a memory cell array of an integrated circuit and conductive lines interconnecting transistors of an external region outside of the memory cell array is provided. The method includes patterning troughs in a dielectric region covering the memory cell array according to a first critical dimension mask. Bitline contacts to a substrate and bitlines are formed in the troughs. Thereafter, conductive lines are formed which consist essentially of at least one material selected from the group consisting of metals and conductive compounds of metals in horizontally oriented patterns patterned by a second critical dimension mask, wherein the conductive lines interconnect the bitlines to transistors of external circuitry outside of the memory cell array, the conductive lines being interconnected to the bitlines only at peripheral edges of the memory cell array.

Abstract: A device having redundant circuit elements is provided with programmable fuse elements on the back surface of the chip. Openings are etched through the chip and connect the circuit elements on the front surface to the fuse elements on the back surface. The fuse elements may be arranged in a grid of lines that are connected to the openings and are read by sequentially activating the lines to activate either a row of fuse elements or a column of fuse elements. Alternatively, bonding pads are provided on the back surface of a chip and are connected to the circuit elements on the front surface of the chip through the openings in the chip.