Abstract: A power conversion method is disclosed. The method includes operating a PFC converter configured to receive three input voltages and provide a DC link voltage between DC link nodes in one of at least two different operating modes, and operating an SR converter coupled to the PFC converter via the DC link nodes in one of at least two different operating modes dependent on an output voltage of the SR converter. Operating the SR converter includes regulating a voltage level of the DC link voltage dependent on a DC link voltage reference, and the at least two different operating modes of the SR converter include a buck mode and a series resonant mode.
Type:
Grant
Filed:
September 9, 2021
Date of Patent:
February 6, 2024
Assignee:
Infineon Technologies Austria AG
Inventors:
Johann Walter Kolar, Yunni Li, Jannik Robin Schaefer
Abstract: A sensor device including a fingerprint sensor and an antenna. The a fingerprint sensor has a silicon-based area sensor, a sensor area, and an electrically conductive contact region arranged laterally adjacent to the sensor area and configured to be touched upon the contact area being touched by a finger in order to bring the finger to a predetermined potential. The antenna is coupled to the fingerprint sensor to inductively couple the fingerprint sensor to a booster antenna.
Abstract: Exemplary embodiments are directed to magnetoresistive sensors and corresponding fabrication methods for magnetoresistive sensors. One example of a magnetoresistive sensor includes a layer stack, wherein the layer stack includes a reference layer having a fixed reference magnetization, wherein the fixed reference magnetization has a first magnetic orientation. The layer stack furthermore includes a magnetically free system of a plurality of layers, wherein the magnetically free system has a magnetically free magnetization, wherein the magnetically free magnetization is variable in the presence of an external magnetic field, and wherein the magnetically free magnetization has a second magnetic orientation in a ground state. The magnetically free system has two ferromagnetic layers and an interlayer, wherein the interlayer is arranged between the two ferromagnetic layers and includes magnesium oxide.
Abstract: A device is configured to receive, from a controller, an instruction requesting data for the device and determine a comparison result value based on a comparison of the data for the device and a reference value. The device is further configured to determine whether to respond to the instruction based on the comparison result value and, in response to a determination to respond to the instruction, output, to the controller, the comparison result value, wherein, to output the comparison result value, the device is configured to refrain from outputting the data for the device.
Type:
Grant
Filed:
July 7, 2022
Date of Patent:
February 6, 2024
Assignee:
Infineon Technologies AG
Inventors:
Markus Ekler, Christian Walther, Christian Heiling
Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.
Type:
Application
Filed:
October 16, 2023
Publication date:
February 1, 2024
Applicant:
Infineon Technologies AG
Inventors:
Edward FUERGUT, Chii Shang HONG, Teck Sim LEE, Bernd SCHMOELZER, Ke Yan TEAN, Lee Shuang WANG
Abstract: In an embodiment, a method includes: receiving raw data from a millimeter-wave radar sensor; generating a first radar-Doppler image based on the raw data; generating a first radar point cloud based on the first radar-Doppler image; using a graph encoder to generate a first graph representation vector indicative of one or more relationships between two or more parts of the target based on the first radar point cloud; generating a first cadence velocity diagram indicative of a periodicity of movement of one or more parts of the target based on the first radar-Doppler image; and classifying an activity of a target based on the first graph representation vector and the first cadence velocity diagram.
Abstract: A method of driving a transistor between switching states includes controlling a transition of a gate voltage at a gate terminal of a transistor during each of a plurality of turn-off switching events to turn off the transistor, wherein the transistor is configured to be turned off according to a desaturation time during each of the plurality of turn-off switching events; measuring a transistor parameter indicative of a voltage slew rate of the transistor for a first turn-off switching event during which the transistor is transitioned from an on state to an off state; and regulating a duration of the desaturation time for a next turn-off switching event based on the measured transistor parameter.
Type:
Application
Filed:
July 28, 2022
Publication date:
February 1, 2024
Applicant:
Infineon Technologies AG
Inventors:
Guang ZENG, Franz-Josef NIEDERNOSTHEIDE, Mark-Matthias BAKRAN, Zheming LI
Abstract: An electronic device includes: an interface configured to receive telemetry information for one or more power semiconductor devices; and a data acquisition and processing unit. The data acquisition and processing unit may be configured to periodically update an estimate of a remaining lifetime of the one or more power semiconductor devices, based on the telemetry information collected during use of the one or more power semiconductor devices and received at the interface. The data acquisition and processing unit may be configured to adjust one or more operating parameters for each of the one or more power semiconductor devices that has reached a predetermined level of degradation as determined by the telemetry information. An electronic system that includes the electronic device is also described.
Type:
Grant
Filed:
July 5, 2022
Date of Patent:
January 30, 2024
Assignee:
Infineon Technologies AG
Inventors:
Wolfgang Budde, Jens de Bock, Daniel Domes, Andreas Lenniger, Bjoern Rentemeister, Stefan Hubert Schmies, Andreas Vetter
Abstract: A method is disclosed. In one example, the method includes bonding a first panel of a first material to a base panel in a first gas atmosphere, wherein multiple hermetically sealed first cavities encapsulating gas of the first gas atmosphere are formed between the first panel and the base panel. The method further includes bonding a second panel of a second material to at least one of the base panel and the first panel, wherein multiple second cavities are formed between the second panel and the at least one of the base panel and the first panel.
Abstract: A touch sensor includes: a transmitter configured to transmit an ultrasonic transmit wave towards a touch structure; a receiver configured to receive an ultrasonic reflected wave produced from the ultrasonic transmit signal being at least partially reflecting by the touch structure; a receiver circuit configured to convert the ultrasonic reflected wave into a measurement signal; the receiver circuit configured to generate an error value representative of a difference between a measured value of the measurement signal and a reference value; a programmable voltage source configured to provide a bias voltage to the transmitter or to the receiver; a controller configured to adjust the bias voltage based on the error value; a measurement circuit configured to measure the DC bias voltage and determine whether a no-touch event or a touch event has occurred at the touch structure based on at least one measurement of the bias voltage.
Abstract: A semiconductor device includes a semiconductor wafer or a single semiconductor chip or die, and a layer stack. The layer stack comprises a first layer comprising NiSi, and a second layer comprising NiV, wherein the second layer is arranged between the first layer and the semiconductor wafer or single semiconductor chip or die.
Type:
Grant
Filed:
March 7, 2022
Date of Patent:
January 30, 2024
Assignee:
Infineon Technologies Austria AG
Inventors:
Paul Frank, Thomas Heinelt, Oliver Schilling, Sven Schmidbauer, Frank Wagner
Abstract: A method of manufacturing a lateral transistor is described. The method includes providing a semiconductor substrate. A dielectric layer is formed over the semiconductor substrate. A gate layer is formed over the dielectric layer. A photoresist layer is applied over the gate layer. The photoresist layer is opened by lithography to form a first opening of a first opening size in the photoresist layer. The first opening is transferred into a second opening of a second opening size, the second opening being either formed in the photoresist layer or in an auxiliary layer. A body region is formed in the semiconductor substrate by dopant implantation. Further the gate layer is structured to form a gate edge. An overlap between the structured gate layer and the body region is controlled by an offset between the first opening size and the second opening size.
Type:
Grant
Filed:
June 24, 2021
Date of Patent:
January 30, 2024
Assignee:
Infineon Technologies Dresden GmbH & Co. KG
Abstract: A method for a radar device is described below. According to an example implementation, the method comprises transmitting an RF transmission signal that comprises a plurality of frequency-modulated chirps, and receiving an RF radar signal and generating a dataset containing in each case a particular number of digital values based on the received RF radar signal. A dataset may in this case be associated with a chirp or a sequence of successive chirps. The method furthermore comprises filtering the dataset by way of a neural network to which the dataset is fed in order to reduce an interfering signal contained therein. A convolutional neural network is used as the neural network.
Type:
Grant
Filed:
March 12, 2020
Date of Patent:
January 30, 2024
Assignee:
Infineon Technologies AG
Inventors:
Paul Meissner, Elmar Messner, Franz Pernkopf, Johanna Rock, Mate Andras Toth
Abstract: A memory device can include a plurality of memory cells for storing data, a memory interface configured to store and retrieve data at the plurality of memory cells, a logic unit comprising digital circuitry configured to perform mathematic and logic operations, and a control circuitry configured to control operation of the memory device.
Abstract: A method for processing a wide band gap semiconductor wafer includes: depositing a support layer including semiconductor material at a back side of a wide band gap semiconductor wafer, the wide band gap semiconductor wafer having a band gap larger than the band gap of silicon; depositing an epitaxial layer at a front side of the wide band gap semiconductor wafer; and splitting the wide band gap semiconductor wafer along a splitting region to obtain a device wafer comprising at least a part of the epitaxial layer, and a remaining wafer comprising the support layer.
Type:
Grant
Filed:
July 22, 2021
Date of Patent:
January 30, 2024
Assignee:
Infineon Technologies AG
Inventors:
Francisco Javier Santos Rodriguez, Günter Denifl, Tobias Hoechbauer, Martin Huber, Wolfgang Lehnert, Roland Rupp, Hans-Joachim Schulze
Abstract: A system includes a first membrane, a second membrane and a third membrane spaced apart from one another, wherein the second membrane is between the first membrane and the third membrane, and the second membrane comprises a plurality of openings, a sealed low pressure chamber between the first membrane and the third membrane, and a plurality of electrodes in the sealed low pressure chamber.
Type:
Grant
Filed:
December 21, 2020
Date of Patent:
January 30, 2024
Assignee:
Infineon Technologies AG
Inventors:
Marc Fueldner, Andreas Wiesbauer, Athanasios Kollias
Abstract: A master is provided which is connected to at least one slave via an interface, wherein the at least one master is designed, in a transmission mode to transfer a valid combination of output data and associated error detection data via the interface, and wherein the at least one master is furthermore designed, in a non-transmission mode, to output an invalid combination of output data and associated error detection data in case of an erroneous output request.
Abstract: Pressure sensors include stacking of sensor capacitors on top of reference capacitors. A pressure cavity may be extended below a bottom electrode. The pressure sensors may include a mechanical link of a top membrane with the bottom electrode in order to form a dual membrane, or a mechanical link of the top membrane, the bottom electrode and an intermediate electrode within a cavity. A pressure sensor includes a first and second pressure sensing portions, each including a first and second rigid electrodes, and a deflectable membrane structure. The second rigid electrode is between the first rigid electrode and the deflectable membrane structure arranged in a vertical configuration. The first and second rigid electrodes of the first and second pressure sensing portions form respective reference capacitors, and the second rigid electrodes and the deflectable membrane structures form respective sensing capacitors.
Abstract: A method is disclosed. The method includes measuring at least one electrical parameter (R, L, C) of at least one wire (10) in a motor vehicle (100) at a certain time instance (ti) to obtain measurement data (M(ti)); comparing the measurement data (M(ti)) with comparative data (C(ti)) held in a data storage (5); and taking a predefined action (63) dependent on the comparing.
Abstract: A method of forming a semiconductor device includes forming a trench in a semiconductor body; at least partially filling the trench with a filling material; introducing dopants into a portion of the filling material; and applying a first thermal processing to the semiconductor body to spread the dopants in the filling material along a vertical direction of the filling material by a diffusion process. The vertical doping profile of the dopants within the doped filling material is shaped during the first thermal processing. Additionally, the dopants are substantially confined to within the trench and substantially do not diffuse from the doped filling material into the semiconductor body during the first thermal processing. A second thermal processing is applied to the semiconductor body after the first thermal processing to cause diffusion of the dopants from the doped filling material into the semiconductor body adjoining the trench.