Abstract: Semiconductor devices and methods of manufacturing the same are provided. The semiconductor devices may have a memory array having two transistor (2T) memory cells, each including a non-volatile memory (NVM) transistor and a high voltage (HV) field-effect transistor (FET) as a select transistor disposed within at least one recess(es). The devices further include a logic area in which HV FETs, input/output (I/) FETs, and low voltage (LV)/core FETs are formed thereon. Other embodiments are also described.

Abstract: A method of forming a semiconductor package includes providing a first metal substrate; and mounting a stacked arrangement on the first metal substrate, the stacked arrangement comprising a semiconductor die, wherein mounting the stacked arrangement includes: providing a first layer of attachment material between the first metal substrate and the stacked arrangement; and providing a second layer of attachment material within the stacked arrangement at an interface with the semiconductor die, wherein at least one of the first and second layers of attachment material is a compressible layer that includes one or more elastomeric elements embedded within a matrix of solder material.

Abstract: A power semiconductor device includes, an active area that conducts load current between first and second load terminal structures, a drift region, and a backside region that includes, inside the active area, first and second backside emitter zones one or both of which includes: first sectors having at least one first region of a second conductivity type contacting the second load terminal structure and a smallest lateral extension of at most 50 ?m; and/or second sectors having a second region of the second conductivity type contacting the second load terminal structure and a smallest lateral extension of at least 50 ?m. The emitter zones differ by at least of: the presence of first and/or second sectors; smallest lateral extension of first and/or second sectors; lateral distance between neighboring first and/or second sectors; smallest lateral extension of the first regions; lateral distance between neighboring first regions within the same first sector.

Abstract: A module includes: an electrically insulative housing; a driver circuit enclosed in the housing and configured to drive a control terminal of a power switch; a wireless communication circuit enclosed in the housing and configured to receive, through the housing, wireless control information transmitted to the module; and a wireless energy receiver enclosed in the housing and configured to receive, through the housing, energy wirelessly transmitted to the module, and to supply power to the driver circuit. The driver circuit is configured to drive the control terminal of the power switch based on the wireless control information received by the wireless communication circuit. A power electronic assembly that incorporates one or more of the modules and a corresponding power conversion control circuit are also described.

Abstract: An apparatus employed in a processing device comprises a processor configured to process data of a predefined data structure. A memory fetch device is coupled to the processor and is configured to determine addresses of the packed data for the processor. The packed data is stored on a memory device that is coupled to the processor. The memory fetch device is further configured to provide output data based on the addresses of the packed data to the processor, where the output data is configured according to the predefine data structure.

Abstract: A Hall sensor is disclosed. The Hall sensor comprises a first Hall element, configured to detect a component of a magnetic field in a first direction a using a sensitive area of the first Hall element. The Hall sensor further comprises a second Hall element, configured to detect a component of the magnetic field in a second direction b using a sensitive area of the second Hall element. The Hall sensor further comprises a conductor track, configured to generate a calibration magnetic field. The calibration magnetic field has a significant component on the sensitive area of the first Hall element in the second direction b. The calibration magnetic field further has a significant component on the sensitive area of the second Hall element in the first direction a.

Abstract: An embedded chip-package is provided. In one example, the embedded chip-package includes a chip, an electrically insulating material at least partially encapsulating the chip, at least one metal layer configured to provide at least one electrically conductive connection to the chip, and an information section. The information section includes coded information about the embedded chip-package, wherein, in the information section, the information is coded as a pattern of electrically conductive portions and electrically insulating portions.

Abstract: Systems, methods, and devices securely boot processors and nonvolatile memories. Methods include implementing, using a controller of a secured nonvolatile memory, a validation operation on a first portion of code stored in a first secured storage region of the secured nonvolatile memory, the validation operation comprising computing a validation value. Methods also include retrieving a second portion of code from a second secured storage region, the second portion of code comprising a pre-computed validation value, the first and second portion of code being associated with booting a processor, and implementing a comparison operation of the validation value and the pre-computed validation value. Methods further include generating, using the controller, a signal based on a result of the comparison operation, the signal being provided to the processor via an interface of the secured nonvolatile memory, and the signal enabling booting of the processor in response to a matching comparison operation.

Abstract: A package is disclosed. In one example, the package comprises a carrier, a first chip with an integrated transistor and comprising a first terminal attached on the carrier, a second terminal, and a third terminal, wherein the first terminal and the third terminal are formed on one main surface of the first chip and the second terminal is formed on an opposing other main surface of the first chip. A conductive structure is attached on the second terminal, an encapsulant is at least partially encapsulating the carrier, the first chip, and the conductive structure, and an insulating layer is arranged on a surface portion of the conductive structure or of the carrier. The surface portion is exposed beyond the encapsulant.

Abstract: The disclosure is directed to the use of an externally-supplied control current to control the adjustment of an internal supply voltage generated via voltage regulator circuitry, which may be identified with an integrated circuit (IC) chip. The configuration of the voltage regulator circuitry functions to establish a linear relationship between the control current and the internal voltage supply. This configuration enables setting the control current to a predetermined value, causing the supply voltage to deviate in a predictable and controllable manner, and thus facilitating verification of the IC chip's internal voltage supply test circuitry. Furthermore, because the control current used for this purpose is relatively small (e.g. on the order of microamps), existing on chip test architecture, which may accommodate such low level currents, may be re-used for the selective routing of the control current for such IC testing.

Abstract: A controller for a power converter, a corresponding power converter and a corresponding method are provided. The controller for a power converter includes a rectifier configured to receive an alternating current input signal and output rectified half waves, an output capacitor and a current control device is coupled between the rectifier and the output capacitor. After reaching a first maximum voltage, power flowing is gradually reduced, and later the current provided to the output capacitor is gradually ramped up.

Abstract: A method can include, for each row of a nonvolatile memory (NVM) cell array, generating a multiply-accumulate (MAC) result for the row by applying input values on bit lines. Each MAC result comprising a summation of an analog current or voltage that is a function of each input value modified by a corresponding weight value stored by the NVM cells of the row. By operation of at least one multiplexer, one of the rows can be connected to an analog-to-digital converter (ADC) circuit to convert the analog current or voltage of the row into a digital MAC value. A storage element of each NVM cell can be configured to store a weight value that can vary between no less than three different values. Corresponding devices and systems are also disclosed.

Abstract: Embodiments of the present disclosure relate to a guiding system for a robot. The guiding system includes a millimeter-wave positioning system and a transmitter. The millimeter-wave positioning system is configured to determine a position of the robot relative to a base station for charging the robot. The transmitter is configured to emit a radar guiding signal for guiding the robot to the base station and to steer the radar guiding signal towards the position of the robot.

Abstract: An inductor device includes a first face, a first inductive path, and magnetic permeable material. The first face couples the inductor device to a circuit board. The first inductive path extends between a first terminal on the first face to a second terminal on the first face. A portion of the first inductive path is exposed on a second face of the inductor device. The second face is disposed opposite the first face. The second face supports dissipation of heat conveyed by the first inductive path from the first face to the second face. The magnetic permeable material is disposed between the first face and the second face and carries magnetic flux associated with the first inductive path.

Abstract: The described techniques address issues associated with electrostatic discharge (ESD) protection for multi-die integrated circuits (ICs). The techniques include the use of two or more semiconductor dies within a multi-die IC, which may include a first semiconductor die without ESD protection but with full ESD exposure. The first semiconductor receives ESD protection via a second semiconductor die that is integrated as part of the same package with the first semiconductor die. The second semiconductor die may be electrically more remote from ESD-exposed pins compared to the first semiconductor die. The first semiconductor die may include integrated passive devices. The second semiconductor die enables ESD protection for both semiconductor dies in the same integrated IC package.

Abstract: An emitter for emitting radiations at a specific wavelength includes a Joule-heated emitting electrical conductor to emit radiations at an emission temperature, a controller to control a variable voltage subjected to the Joule-heated emitting electrical conductor and modulated according to a duty cycle, the duty cycle being variable between a high-average power duty cycle during hot periods, so that the Joule-heated emitting electrical conductor is subjected to a high-average power to reach and maintain the emission temperature; and a low-average power duty cycle during cold periods alternated to the hot periods, so that the Joule-heated emitting electrical conductor is subjected to a low-average power to reach a temperature smaller than the emission temperature, wherein the high-average power duty cycle and the low-average power duty cycle is defined based on a temperature-indicative measured value indicative of the ambient temperature as measured.

Abstract: An apparatus for detecting a specular surface in a scene is provided. The apparatus includes an illumination device configured to emit polarized light towards the scene. The apparatus further includes an imaging system configured to capture a first image of the scene based on light emanating from the scene. The light emanating from the scene includes one or more reflection of the emitted polarized light. The imaging system is further configured to capture a second image of the scene based on filtered light. The apparatus further includes a polarization filter configured to generate the filtered light by filtering the light emanating from the scene. The apparatus further includes processing circuitry configured to determine presence of the specular surface in the scene based on a comparison of the first image and the second image.

Abstract: This disclosure includes novel ways of implementing a power supply that powers a load. More specifically, a power supply includes a bidirectional power converter and a controller. The controller monitors a magnitude of an input voltage supplied from an input voltage source to a load. Based on a magnitude of the input voltage, the controller switches between a first mode of operating the bidirectional power converter to charge an energy storage resource using (a portion of power provided by) the input voltage and a second mode of producing a backup voltage from the energy storage resource to power the load as a substitute to the input voltage such as when the input voltage is below a threshold value.

Abstract: The innovative concept described herein relates to a magnetic angle sensor system having a rotatable shaft, a permanent magnet coupled to the rotatable shaft, and a magnetic field sensor arranged opposite the permanent magnet, wherein the magnetic field sensor is configured to detect a magnetic field prevailing in its detection region. The magnetic angle sensor system comprises means for reducing and/or compensating for an inhomogeneous stray field component of a per se homogeneous external magnetic stray field.

Abstract: A semiconductor device package comprises an electrically conductive carrier, a semiconductor die disposed on the carrier, an encapsulant encapsulating part of the carrier and the semiconductor die, an electrically insulating and thermally conductive interface structure, in particular covering an exposed surface portion of the carrier and a connected surface portion of the encapsulant, wherein the interface structure comprises a glass transition temperature in a range between ?40° C. to 150° C.