Abstract: A semiconductor module includes a substrate, a semiconductor die arranged on the substrate, at least one first bond wire loop, wherein both ends of the at least one first bond wire loop are arranged on and coupled to a first electrode of the semiconductor die, and a molded body encapsulating the semiconductor die, wherein a top portion of the at least one first bond wire loop is exposed from a first side of the molded body.

Abstract: A molded semiconductor package includes: a mold compound; a metal substrate partly embedded in the mold compound; at least one first metal lead partly embedded in the mold compound; an inlay embedded in the mold compound, the inlay comprising a semiconductor die embedded in an electrically insulating body, a first metal structure attached to a first side of the semiconductor die, and a second metal structure attached to a second side of the semiconductor die; and a metal clip at least partly embedded in the mold compound and connecting the second metal structure to the at least one first metal lead. The semiconductor die has a maximum junction temperature higher than a glass transition temperature of the mold compound, the electrically insulating body has a glass transition temperature at or above the maximum junction temperature of the semiconductor die, and the metal substrate is attached to the first metal structure.

Abstract: An apparatus for testing semiconductor devices is disclosed. In one example, the apparatus includes a rolling contactor comprising a first cylindrical rotatable holder, a plurality of test pin sets, each one of the test pin sets being connected to the cylindrical rotatable holder. Each one of the test pin sets comprises a plurality of test pins, and a substrate configured to support a plurality of semiconductor devices. The semiconductor devices comprising one or more contact elements on a main surface thereof remote from the substrate, wherein the first cylindrical rotatable holder and the substrate are arranged relative to each other so that due to a rotating movement of the first cylindrical rotatable holder the test pins of the test pin sets are successively contacted with the contact elements of the semiconductor devices.

Abstract: A semiconductor device includes a transistor that has: a drift region of a first conductivity type in a semiconductor substrate having a first main surface; a body region of a second conductivity type between the drift region and the first main surface; a plurality of trenches in the first main surface and patterning the semiconductor substrate into a plurality of mesas including a first mesa and a plurality of dummy mesas, the plurality of trenches including an active trench and a plurality of dummy trenches arranged in a row; a gate electrode arranged in the active trench; and a source region of the first conductivity type in the first mesa. The first mesa is arranged adjacent to the active trench. A dummy mesa is arranged between each adjacent pair of the dummy trenches. The dummy mesas do not carry load current during an on-state of the transistor.

Abstract: A printed circuit board and method of manufacturing a printed circuit board are disclosed. In one example, the method comprises embedding an electronic component in a laminate, and protecting the electronic component against electrostatic discharge during at least part of the manufacturing process by an electrically conductive electrostatic discharge protection structure integrated in the laminate and connected to the electronic component.

Abstract: A method of operating a memory circuit is disclosed. The memory circuit includes a memory array having a memory portion and a spare portion. The method includes receiving a first write command to a first memory address, where the first memory address has a status of being mapped to a first spare memory address, and where the first memory address corresponds to a first memory location in the memory portion and the first spare memory address corresponds to a first spare memory location in the spare portion. The method also includes performing, in response to the first write command, a first write operation by attempting to write first data to the first memory location, determining if the first write operation is successful, and unmapping, in response to the first write operation of being successful, the first memory address from the first spare memory address.

Abstract: A method of manufacturing a chip structure is provided. The method includes attaching a chip to a chip carrier using a chip attach layer, wherein the chip attach layer comprises a metal having a first melting point. The chip comprises a solder layer and the chip carrier comprises a further solder layer, the solder layer and/or the further solder layer comprising a respective solder material having a second melting point lower than the first melting point. An intermetallic phase is formed between the solder material and metal of the chip attach layer by melting the solder material having the second melting point.

Abstract: A method comprises applying a driver voltage to an electrostatic comb drive of an MEMS apparatus and overlaying the driver voltage with a periodic voltage signal. The method further comprises determining a torsion angle of a mirror body of the MEMS apparatus based on the periodic voltage signal.

Abstract: A chip package includes a chip with at least one contact pad, a contact structure formed from at least one continuous longitudinally extended electrically conductive element by attaching the conductive element to the contact pad in at least three contact positions, wherein the conductive element bends away from the contact pad between pairs of consecutive contact positions, and an encapsulation partially encapsulating the contact structure, wherein the encapsulation includes an outer surface facing away from the chip, and wherein the contact structure is partially exposed at the outer surface.

Abstract: A circuit includes a cross-talk compensation component including a power profile reconstruction component for reconstructing the power profile of a digital microphone coupled to a microelectromechanical (MEMS) device, wherein the power profile represents power consumption of the digital microphone over time between at least two operational modes of the digital microphone, and a reconstruction filter for modeling thermal and/or acoustic properties of the digital microphone; and a subtractor having a first input for receiving a signal from the digital microphone, a second input coupled to the cross-talk compensation component, and an output for providing a digital output signal.

Abstract: A method includes providing a semiconductor body, forming a thermosensitive element on or within the semiconductor body, forming a structured laser-reflective mask on the upper surface of the semiconductor body that covers the thermosensitive element and includes first and second openings, and performing a laser thermal annealing process that transmits laser energy through the first and second openings and into the semiconductor body, wherein the thermosensitive element comprises a critical temperature at which the thermosensitive element is irreparably damaged, wherein the laser thermal annealing process brings portions of the semiconductor body that are underneath the first and second openings to above the critical temperature, and wherein during the laser thermal annealing process the thermosensitive element remains below the critical temperature.

Abstract: A driver circuit is configured control one or more bypass transistors. The driver circuit includes a primary supply input connection configured to supply the driver circuit with power from a set of battery cells. The set of battery cells is configured to supply power to a load via a power delivery circuit. The driver circuit also includes one or more secondary supply input connections. The driver circuit is configured to receive information indicating whether an error condition is present in the power delivery circuit and control, based on the error condition being present in the power delivery circuit, the one or more bypass transistors to define a bypass current path. The driver circuit is also configured to receive, via a secondary supply input connection of the one or more secondary supply input connections, power from the bypass current path.

Abstract: A torque measurement system includes a first rotatable carrier structure and a second rotatable carrier structure mechanically coupled to a shaft; a first metamaterial track coupled to and configured to co-rotate with the first rotatable carrier structure; a second metamaterial track coupled to and configured to co-rotate with the second rotatable carrier structure; and a low-friction material arranged between the first and the second rotatable carrier structures. The first and the second metamaterial tracks are spaced apart by a predetermined distance and are mutually coupled to each other by a torque-dependent coupling. Responsive to a torque applied to the shaft, the first metamaterial track is configured to undergo a rotational shift relative to the second metamaterial track. The low-friction material provides a low-friction rotational shift between the first rotatable carrier structure and the second rotatable carrier structure such that the predetermined distance is constant during the rotational shift.

Abstract: A radio frequency integrated circuit (RFIC) device includes: a first RF input/output (I/O) terminal; a second RF I/O terminal, where the first and the second RF I/O terminals are configured to transmit or receive an RF signal; a capacitor coupled between the first and the second RF I/O terminals; a first coil coupled between the first and the second RF I/O terminals, where the first coil is configured to provide ESD protection to the capacitor during a first ESD event; and a fast transient ESD protection circuit coupled between the first and the second RF I/O terminals, where the fast transient ESD protection circuit is configured to provide ESD protection to the capacitor during a second ESD event different from the first ESD event, where a first rise time of the first ESD event is longer than a second rise time of the second ESD event.

Abstract: An exemplary embodiment of a sensor system includes a magnet system which is designed to generate a magnetic field. Furthermore, the sensor system includes a first magnetic field sensor which is movable in a first direction relative to the magnet system and has a first distance from the magnet system in a second direction perpendicular to the first direction. The sensor system also includes a second magnetic field sensor which is movable in the first direction relative to the magnet system and has a second distance from the magnet system in the second direction, the second distance being greater than the first distance.

Abstract: A radio frequency switch device includes a first transistor and a second transistor; a compensation network coupled between a body terminal of the first transistor and a source/drain terminal of the second transistor; and a bootstrapping network having a first terminal coupled to a first bias terminal, a second terminal coupled to a gate terminal of the first transistor, and a third terminal coupled to the body terminal of the first transistor, wherein the bootstrapping network establishes a low impedance path between the gate terminal and the body terminal of the first transistor in response to a first voltage value of the first bias terminal, and wherein the bootstrapping network establishes a high impedance path between the gate terminal and the body terminal of the first transistor in response to a second voltage value of the first bias terminal.

Abstract: A carrier for carrying an electronic component of a package is disclosed. In one example, the carrier comprises a front side being provided with a horizontal component-sided area, and a back side opposing said front side and being provided with a horizontal back side area. A size of the horizontal back side area is larger than a size of the horizontal component-sided area.

Abstract: An approach for correcting at least one byte error in a binary sequence is proposed, the binary sequence comprising a plurality of bytes and being a code word of an error code in the error-free case. The approach comprises the steps of: (i) determining at least one byte error position signal which specifies whether or not a byte of the binary sequence is erroneous, (ii) determining at least one byte error correction value, based on which an erroneous byte position identified by means of the byte error position signal is correctable, the at least one byte error correction value being determined by virtue of a first value and a second value being determined for each of at least two byte positions based on a coefficient of the locator polynomial, and (iii) correcting the at least one byte error based on the at least one byte error correction value.

Abstract: Compiling a compression function of a lattice-based cryptographic mechanism by (i) basing the compression function on a lossy compression function, (ii) determining an error based on a loss introduced by an integer division, and (iii) determining an output of the compression function based on the error.

Abstract: An integrated circuit includes a transistor, a first metallization layer above the transistor and electrically connected to the transistor, and a phase change switch, wherein at least a part of the phase change switch is provided below the first metallization layer, wherein the first metallization layer is provided laterally adjacent to the phase change switch, wherein the phase change switch comprises a heater, and wherein the heater and a part of the transistor are each provided in a lower-level interconnect layer of the integrated circuit.