Abstract: An apparatus includes a semiconductor-based substrate with a functional structure that is formed in or on the semiconductor-based substrate. The apparatus includes a frame structure surrounding the functional structure and includes a coating that covers the functional structure and is delimited by the frame structure.

Abstract: A method for fabricating a semiconductor device includes providing a semiconductor die, arranging an electrical connector over the semiconductor die, the electrical connector including a conductive core, an absorbing feature arranged on a first side of the conductive core, and a solder layer arranged on a second side of the conductive core, opposite the first side and facing the semiconductor die, and soldering the electrical connector onto the semiconductor die by heating the solder layer with a laser, wherein the laser irradiates the absorbing feature and absorbed energy is transferred from the absorbing feature through the conductive core to the solder layer.

Abstract: In accordance with an embodiment, a circuit includes: a pass transistor drive circuit including an digital input, and at least one output configured to be coupled to at least one pass transistor; a digital feedback circuit having a first analog input configured to be coupled to the at least one pass transistor, and a digital output coupled to the digital input of the pass transistor drive circuit; and an analog feedback circuit including a second analog input configured to be coupled to the at least one pass transistor, and an analog output coupled to an over voltage node of the pass transistor drive circuit, where the analog feedback circuit has a DC gain greater than zero.

Abstract: A microfabricated structure includes a perforated stator; a first isolation layer on a first surface of the perforated stator; a second isolation layer on a second surface of the perforated stator; a first membrane on the first isolation layer; a second membrane on the second isolation layer; and a pillar coupled between the first membrane and the second membrane, wherein the first isolation layer includes a first tapered edge portion having a common surface with the first membrane, wherein the second isolation layer includes a first tapered edge portion having a common surface with the second membrane, and wherein an endpoint of the first tapered edge portion of the first isolation layer is laterally offset with respect to an endpoint of the first tapered edge portion of the second isolation layer.

Abstract: A semiconductor device includes: a semiconductor substrate; a first gate trench and a second gate trench both extending from a first main surface of the semiconductor substrate into the semiconductor substrate; a semiconductor mesa delimited by the first and second gate trenches; and a field plate trench extending from the first main surface through the semiconductor mesa. The field plate trench includes a field plate separated from each sidewall and a bottom of the field plate trench by an air gap. The field plate is anchored to the semiconductor substrate at the bottom of the field plate trench by an electrically insulative material that occupies a space in a central part of the field plate, the electrically insulative material spanning the air gap to contact the semiconductor substrate at the bottom of the field plate trench. Methods of producing the semiconductor device are also described.

Abstract: A data storage device comprises a plurality of storage elements, each storage element configured for storing a piece of information. The plurality of storage elements is accessible as a plurality of word sets, each word set comprising a set of storage elements, and is accessible as a plurality of slice sets, each slice set comprising a set of storage elements. Each storage element is a part of a word set and a part of a slice set. The device further comprises a control unit configured for obtaining word information and slice information and for executing a write operation to parallelly write the word information into a first word set of the plurality of word sets and the slice information into a first slice set of the plurality of slice sets, wherein the first word set and the first slice set comprise a common storage element defined by an overlap of the first word set and the first slice set in a layout of the plurality of storage elements.

Abstract: A MEMS device includes a package for providing an inner volume, a MEMS microphone arranged in the inner volume, a sound port through the package to the inner volume, and a passive acoustic attenuation filter acoustically coupled to the sound port.

Abstract: A molded semiconductor package includes: a semiconductor die; a substrate attached to a first side of the semiconductor die; a plurality of leads electrically connected to a pad at a second side of the semiconductor die opposite the first side; a heat sink clip thermally coupled to the pad; and a molding compound encapsulating the semiconductor die, part of the leads, part of the heat sink clip, and at least part of the substrate. The molding compound has a first main side, a second main side opposite the first main side and at which the substrate is disposed, and an edge extending between the first main side and the second main side. The leads protrude from opposing first and second faces of the edge of the molding compound. The heat sink clip protrudes from opposing third and fourth faces of the edge of the molding compound.

Abstract: Signal processing circuitry includes at least one processor configured to obtain a digitized radar signal, and further configured, for one or more iterations, to: determine a first power of at least one first signal sample of the radar signal; determine a second power of at least one second signal sample of the radar signal, the at least one second signal sample being subsequent in time to the at least one first signal sample; and determine a difference value between the second power and the first power. The at least one processor further configured to detecting a burst interference signal occurring within the radar signal based on the one or more difference values from the one or more iterations.

Abstract: A power connector is provided that is configured to conduct a current and includes a conductive frame including a base structure, an extension structure, and a cap structure that define a current path for the current. The base structure is configured to be coupled to a current supply for receiving the current therefrom. The cap structure is configured to be coupled to an electrical interface of a device to be supplied with the current and outputs the current from the connector to the electrical interface of the device. The extension structure is coupled to and vertically extends between the base structure and the cap structure. The extension structure includes a current constriction region that is configured to cause a defined magnetic field of the current flowing through the current constriction region at a predefined position.

Abstract: Overload detection and protection for power switch circuits. For circuits with faster switching speed, fast fault detection and response to a detected overload condition may be desirable. Detection circuitry may monitor a voltage on the control terminal of one or more power switches. Based on empirical measurements, in an overload condition of a power switch circuit, e.g., a half-bridge circuit, the voltage at the control terminal may increase, and in some examples, increase to a magnitude that is greater than a supply voltage. A comparator may detect a voltage increase that exceeds a voltage magnitude threshold, output an indication to control circuitry for the power switch circuit, and the control circuitry may take action to protect the rest of the circuitry, such as reduce voltage or shut off the power switch circuit.

Abstract: A semiconductor package includes a semiconductor chip, an encapsulation body encapsulating the semiconductor chip, and a metal sheet having a first sheet surface and an opposite second sheet surface. The first sheet surface is exposed at the encapsulation body. The semiconductor chip is arranged at the second sheet surface. The first sheet surface has a pattern having first subdivisions having a first average roughness and second subdivisions having a second average roughness. The first average roughness is greater than the second average roughness.

Abstract: In an embodiment, a semiconductor device includes: a main transistor having a load path; a sense transistor configured to sense a main current flowing in the load path of the main transistor; and a bypass diode structure configured to protect the sense transistor and electrically coupled in parallel with the sense transistor. A sense transistor cell of the sense transistor includes a sense trench and a sense mesa. The sense trench and a bypass diode trench of the bypass diode structure form a common trench. The sense mesa and a bypass diode mesa of the bypass diode structure form a common mesa.

Abstract: According to an embodiment, a security controller is described comprising a memory storing data elements of a data array and a processing circuit configured to determine a power of two such that number of data elements is higher than the power of two but at most equal to double the power of two, determine random first and second integers, change indices of a predefined sequence of indices, comprising performing a first change of the index according to a first permutation if it is lower than the power of two, performing a second change of the index by adding a third integer modulo data array length and performing a third change of the index by a second permutation if it is, following the second change, lower than the power of two, and process the data elements in an order of the changed indices.

Abstract: A gate charge profiler for a power transistor may include a voltage comparator unit and a timer unit. An input signal may control a gate drive current input to a gate of the power transistor to control conduction between a drain and a source of the power transistor. The voltage comparator unit may be configured to compare an input voltage and a threshold voltage, and to output a comparison signal. The input voltage may be a drain-source voltage across the drain and the source of the power transistor or a gate-source voltage across the gate and the source of the power transistor. The timer unit may be configured to output a time value based on input of a transition of the input signal and input of the comparison signal.

Abstract: Systems, methods, and circuitries are disclosed for compressing radar data. In one example, a method includes storing radar data in a memory, the radar data being stored in a data cube having a slow-time dimension, a fast-time dimension, and a channel dimension. The data cube is divided into one or more zones. For each zone a number of data matrices is selected based on a compression factor. Sets of data matrices containing the number of data matrices are formed and, for each set of data matrices, for each data matrix, the data vectors are coded to generate a coded data matrix. A coding for data vectors in a data matrix is the same and a coding for different data matrices is different. The coded data matrices are combined to generate a compressed data matrix for the zone and the compressed data matrices for the one or more zones are stored.

Abstract: A method of forming a semiconductor device includes providing a substrate that comprises a metal region, forming an encapsulant body of electrically insulating material on an upper surface of the metal region, forming an opening in the encapsulant body, and inserting a press-fit connector into the opening, wherein after inserting the press-fit connector into the opening, the press-fit connector is securely retained to the substrate and an interfacing end of the press-fit connector is electrically accessible.

Abstract: A current sensor system includes a magnetic field sensor including a chip plane, a first set of sensor elements sensitive to a first magnetic field component that is aligned in a first direction that is parallel to the chip plane, and a second set of sensor elements sensitive to a second magnetic field component that is aligned in a second direction that is perpendicular to the chip plane; and three conductor structures arranged in parallel to each other and configured to carry a current parallel or antiparallel to a third direction that is perpendicular to the first direction and to the second direction. The three conductor structures generate three magnetic fields based on the current flowing therethrough, where the three magnetic fields produce a first magnetic field distribution of the first magnetic field component and a second magnetic field distribution of the second magnetic field component.

Abstract: A control circuit, a power supply including a control circuit, and a method are disclosed. The control circuit is configured to activate a second output capacitor connected in parallel with a first output capacitor of a power supply when the power supply is in a normal operating mode, and deactivate the second output capacitor when the power supply is in a standby mode.

Abstract: A method of calibrating an analog front end (AFE) filter of a radio frequency integrated circuit (RFIC) includes: making a first measurement of the RFIC at a first measuring frequency while the AFE filter is bypassed; generating a first amplitude estimate and a first phase estimate at the first measuring frequency using the first measurement; making a second measurement of the RFIC at the first measuring frequency while the AFE filter is turned on; generating a second amplitude estimate and a second phase estimate at the first measuring frequency using the second measurement; and calculating a frequency response of the AFE filter at the first measuring frequency, which includes calculating an amplitude response of the AFE filter based on the second amplitude estimate and the first amplitude estimate; and calculating a phase response of the filter based on the first phase estimate and the second phase estimate.