Abstract: A transmitter device of a bus-based communication system may add one or more padding bits, associated with providing traffic flow confidentiality for communication of a payload on a communication bus, either to the payload on a transport layer, or to one or more first frames on a data link layer. The one or more first frames may include a transport layer payload associated with the payload. The transmitter device may transmit one or more second frames, including a data link layer payload associated with the one or more first frames, on the communication bus. A receiver device of the bus-based communication system may receive the one or more second frames on the communication bus. The receiver device may process the one or more padding bits from either the one or more first frames on the data link layer, or from the payload on the transport layer.

Abstract: In an embodiment, a method for forming a microfabricated structure includes depositing a first membrane on a substrate, depositing a first isolation layer on the first membrane, depositing a stator layer on the first isolation layer, forming a perforated stator from the stator layer, wherein the first isolation layer is disposed on a first surface of the perforated stator, depositing a second isolation layer on a second surface of the perforated stator and depositing a second membrane on the second isolation layer, including depositing a pillar coupled between the first membrane and the second membrane, wherein the first isolation layer includes a first glass layer having a low etch rate, and a second glass layer having a high etch rate embedded in the first glass layer.

Abstract: A magnetic sensor system includes a magnetoresistive sensor comprising a magnetic free layer having a sensing plane and a magnetically-free magnetization arranged within the sensing plane, where the magnetically-free magnetization is variable in a presence of an in-plane magnetic field that is aligned with the sensing plane; and a ferromagnetic disc having a magnetic vortex in a ground state, wherein the magnetic vortex is configured to react to an out-of-plane magnetic field and generate a stray field in response to the out-of-plane magnetic field being applied to the ferromagnetic disc. The stray field has an in-plane magnetic field component that is proportional to the out-of-plane magnetic field. The magnetic free layer is configured to receive the in-plane magnetic field component of the stray field. The magnetically-free magnetization is configured to change based on the in-plane magnetic field component of the stray field.

Abstract: Described are solder stop features for electronic devices. An electronic device may include an electrically insulative substrate, a metallization on the electrically insulative substrate, a metal structure attached to a first main surface of the metallization via a solder joint, and a concavity formed in a sidewall of the metallization. The concavity is adjacent at least part of the solder joint and forms a solder stop. A first section of the metal structure is spaced apart from both the metallization and solder joint in a vertical direction that is perpendicular to the first main surface of the metallization. A linear dimension of the concavity in a horizontal direction that is coplanar with the metallization is at least twice the distance by which the first section of the metal structure is spaced apart from the first main surface of the metallization in the vertical direction. Additional solder stop embodiments are described.

Abstract: A power semiconductor device includes an active region with power cells, each configured to conduct a load current portion between first and second load terminals. Each power cell includes: trenches and mesas laterally confined by the trenches and in a vertical direction adjoining a drift region. The mesas include an active mesa having a source region of a first conductivity type and a body region of a second conductivity type separating the source region from the drift region. Both the source and body region are electrically connected to the first load terminal. At least one trench adjacent to the active mesa is configured to induce a conductive channel in the active mesa. A punch through structure s electrically separated from the active mesa by at least one separation stack.

Abstract: In accordance with an embodiment, a method for characterizing a non-volatile memory, includes: applying a first voltage on a word line conductively coupled to a non-volatile memory cell and measuring a current flowing through the non-volatile memory cell in response to applying the first voltage. Measuring the current includes: using a sense amplifier, comparing the current flowing through the non-volatile memory cell with a plurality of different first currents generated by an adjustable current source while applying the same first voltage on the word line, and determining the measured current based on the comparing.

Abstract: A circuit arrangement for driving a semiconductor switch includes an undervoltage detection circuit to indicate an undervoltage state when a supply voltage falls below a voltage threshold value. A temperature detection circuit indicates that a temperature of a semiconductor switch exceeds a temperature threshold value. A control circuit for driving the semiconductor switch deactivates the semiconductor switch when the undervoltage detection circuit indicates an undervoltage state, and to reactivate the semiconductor switch when the undervoltage detection circuit no longer indicates an undervoltage state. In this case, the reactivation is delayed by a defined delay time when the semiconductor switch was previously deactivated due to an undervoltage state and the temperature detection circuit indicates that the temperature of the semiconductor switch exceeds the temperature threshold value.

Abstract: A circuit includes a power transistor having a main current path between a first supply node and an output pin for connecting a load. A resistance formed by a chip metallization is arranged between the main current path of the power transistor and the output pin. The circuit includes a current measuring circuit coupled to the power transistor and including a sense transistor coupled to the power transistor. The current measuring circuit delivers a measurement current representing a load current flowing through the power transistor. An amplifier circuit generates an amplifier output signal representing the voltage across the resistance, and a control circuit outputs a signal representing the measurement current in a first mode and a signal dependent on the amplifier output signal in a second mode.

Abstract: Signal processing circuitry includes at least one processor configured to obtain a digitized radar signal, and further configured, for one or more iterations, to: determine a first power of at least one first signal sample of the radar signal; determine a second power of at least one second signal sample of the radar signal, the at least one second signal sample being subsequent in time to the at least one first signal sample; and determine a difference value between the second power and the first power. The at least one processor further configured to detecting a burst interference signal occurring within the radar signal based on the one or more difference values from the one or more iterations.

Abstract: In an embodiment, a method includes: obtaining one or more radar measurement frames, each one of the one or more radar measurement frames including respective data samples acquired by a radar sensor monitoring a scene; for each one of the one or more radar measurement frames, determining a respective 2-D angular intensity map of the scene based on the respective radar measurement frame; and performing a people counting operation based on the one or more 2-D angular intensity maps determined for the one or more radar measurement frames to determine a people count for the scene.

Abstract: A method for monitoring an RF receiver includes generating of a digital test signal based on a signal, wherein the digital test signal includes a stream of digital test samples having a digital test sample; generating a monitoring signal based on the digital test signal; and coupling of the monitoring signal into a receiver path. The monitoring signal is processed in the receiver path to generate a processed monitoring signal and a stream of digital monitoring samples representing the processed monitoring signal. Information is determined indicating at least one property related to the receiver path based on a processing of a set of digital monitoring samples of the stream of digital monitoring samples. The set of digital monitoring samples includes a digital monitoring sample. The method further includes controlling the RF receiver such that the digital monitoring sample is generated a predetermined time duration after generating the digital test sample.

Abstract: This disclosure describes circuits and techniques for determining inductance on an electrical line. In some examples, a method comprises charging a capacitor in time steps to a voltage level; counting a number of the time steps to the voltage level, wherein the number of the time steps defines a coarse measurement inductance of the electrical line; measuring a charging rate associated with charging the capacitor within a measurement window that is defined at the voltage level, wherein the charging rate associated with charging the capacitor within the measurement window defines a fine measurement of the inductance of the electrical line; and outputting an indication of the number of time steps and an indication of the charging rate associated with charging the capacitor within the measurement window.

Abstract: A power semiconductor device is proposed. The vertical power semiconductor device includes a silicon carbide (SiC) semiconductor body having a first surface and a second surface opposite to the first surface. The SiC semiconductor body includes a transistor cell area comprising gate structures, a gate pad area, and an interconnection area electrically coupling a gate electrode of the gate structures and a gate pad of the gate pad area via a gate interconnection. The vertical power semiconductor device further includes a source or emitter electrode. The vertical power semiconductor device further includes a first interlayer dielectric comprising a first interface to the source or emitter electrode and a second interface to at least one of the gate electrode, or the gate interconnection, or the gate pad, and wherein a conduction band offset at the first interface ranges from 1 eV to 2.5 eV.

Abstract: A carrier for a leadless package is disclosed. In one example, the carrier comprises a component mounting structure for mounting an electronic component thereon, and a plurality of leads arranged around at least part of the component mounting structure, wherein corner leads of said leads are located closer to at least one corner of said component mounting structure than intermediate leads of said leads located farther away from said at least one corner than said corner leads, wherein said corner leads have a larger width along a respective edge of the component mounting structure compared with a smaller width of said intermediate leads, and wherein at least said corner leads comprise a lead tip inspection feature.

Abstract: A signal adjustor receives a first signal such as feedback associated with generation of an output voltage. The output voltage is regulated based on a selected setpoint reference voltage. The signal adjustor maps a magnitude of the selected setpoint reference voltage to a first set of signal adjustment information amongst multiple sets of signal adjustment information. The signal adjustor then applies the first signal adjustment information to the first signal to produce a second signal.

Abstract: A power converter includes: a solid-state transformer having a DC input and isolated DC outputs; a half bridge converter stage for each isolated DC output of the solid-state transformer, wherein an input of each half bridge converter stage is connected to the corresponding isolated DC output and an output of the half bridge converter stages are electrically connected in a cascade configuration; an output inductor shared by the half bridge converter stages and configured to deliver an output current; and a controller configured to implement phase shift control of the half bridge converter stages relative to one another, based on the number of half bridge converter stages and an output voltage of the power converter being regulated, such that each half bridge converter stage processes the full output current but only a fraction of the output voltage. Methods of controlling the power converter are also described.

Abstract: According to an embodiment of a semiconductor device, the device includes: a transistor or diode device formed in a semiconductor substrate; an insulating material at least partially covering a lateral drift zone of the transistor or diode device or a termination region; and a fill pattern disposed over the lateral drift zone or termination region, the fill pattern having a variable density that follows equipotential lines of an electric field distribution expected between the fill pattern at a surface of the lateral drift zone or termination region during operation of the semiconductor device. Corresponding methods of producing the semiconductor device are also described.

Abstract: A method of manufacturing a package includes forming an adhesion promoter on at least part of an electronic component. The adhesion promoter is a morphological adhesion promoter including a morphological structure having a plurality of openings. The method further includes at least partially encapsulating the electronic component with an inorganic encapsulant with the adhesion promoter in between. The adhesion promoter enhances adhesion between at least part of the electronic component and the encapsulant.

Abstract: A semiconductor chip includes an electronic hardware circuitry device that includes a plurality of partitionable hardware resources that each includes a corresponding resource allocation state. The electronic hardware circuitry includes a logic control circuit to control access to the plurality of hardware resources based on the respective resource allocation states of the hardware resources and based on input from one or more authorized agents. The semiconductor chip further includes a processor core to implement a plurality of software applications belonging to a first group or to a second group, each of the plurality of applications configured to access and interact with at least one corresponding hardware resource assigned to the respective application, implement assigning software agents each authorized and configured to cause the electronic hardware circuitry device to assign one or more unassigned hardware resources only to one or more of the software applications belonging to certain groups.

Abstract: Circuits, devices and systems that include a low voltage test for common mode transient immunity (CMTI). The CMTI test of this disclosure may be used in a variety of applications, such as a data transmission circuit configured to communicate across galvanic isolation. A differential circuit may include two signal paths. For robust common mode transient rejection, the first signal path should be the same as the second signal path. Differences in the resistance, inductance, and capacitance between the two signal paths may result in common mode noise being measured as a differential signal at the output terminals. Devices according to the techniques of this disclosure are configured to enter a test mode to conduct a low voltage test that outputs a measurement of CMTI at any phase of production or field use.