Abstract: A radio frequency switch device includes a first transistor and a second transistor; a compensation network coupled between a body terminal of the first transistor and a source/drain terminal of the second transistor; and a bootstrapping network having a first terminal coupled to a first bias terminal, a second terminal coupled to a gate terminal of the first transistor, and a third terminal coupled to the body terminal of the first transistor, wherein the bootstrapping network establishes a low impedance path between the gate terminal and the body terminal of the first transistor in response to a first voltage value of the first bias terminal, and wherein the bootstrapping network establishes a high impedance path between the gate terminal and the body terminal of the first transistor in response to a second voltage value of the first bias terminal.

Abstract: A semiconductor device includes: a carrier including an electronic circuit; a plurality of semiconductor chip packages mounted on the carrier, each of the chip packages including an encapsulation encapsulating the semiconductor chip, a plurality of contact structures electrically connecting the semiconductor chip with the electronic circuit, and at least one cooling structure protruding from the encapsulation; and a cooling element thermally conductively connected to at least one cooling structure of each of at least two of the plurality of semiconductor chip packages.

Abstract: A redundancy system includes a first computational device and a second computational device each configured to receive at least one input and to generate a first output and a second output, respectively, based on the at least one input; a random sequence generator configured to generate a random bit sequence; a random delay selector configured to determine a random delay based on the random bit sequence; a first random delay circuit configured to delay outputting the at least one input to the first computational device based on the random delay; a second random delay circuit configured to delay outputting the second output based on the random delay; and a fault detection circuit configured to receive the first output and the delayed second output, and to generate a comparison result based on comparing the first input to the delayed second output.

Abstract: This disclosure includes novel ways of implementing a power supply that powers a load. A main battery source produces a main battery voltage; each of multiple auxiliary battery sources in a set produces a respective auxiliary battery voltage. A controller initially sets a battery supply voltage to the main battery voltage, the main battery voltage is supplied to a power converter. The controller then monitors a magnitude of the battery supply voltage and adjusts the battery supply voltage supplied to the power converter based on a comparison of the magnitude of the battery supply voltage with respect to a threshold level. The adjusted battery supply voltage is provided from a serial connection of the main battery source and a first auxiliary battery source in the set.

Abstract: A radio frequency (RF) system includes a radar monolithic microwave integrated circuit (MMIC), which includes: a phase detector including a test input port, and a monitoring input port, wherein the phase detector is configured to generate an output signal that represents a phase difference between a test signal received at the test input port and a monitoring signal received at the monitoring input port; a test signal path including at least one active component, the test signal path configured to receive a local oscillator signal and provide the local oscillator signal as the test signal to the test input port during a first measurement interval; and a passive signal path configured to receive the local oscillator signal and provide the local oscillator signal to the monitoring input port as the monitoring signal during the first measurement interval.

Abstract: A magnetic field sensor package includes a sensor housing; a first sensor chip having an integrated first differential magnetic field sensor circuit, the first sensor chip being arranged in the sensor housing; a second sensor chip having an integrated second differential magnetic field sensor circuit, the second sensor chip being arranged in the sensor housing; a common leadframe arranged in the sensor housing and interposed between the first sensor chip and the second sensor chip; and an insulating layer arranged in the sensor housing interposed between the first sensor chip and the common leadframe. The first sensor chip is coupled to the common leadframe via the insulating layer. Additionally, the insulating layer electrically insulates the first sensor chip from the common leadframe such that the first sensor chip and the second sensor chip are galvanically decoupled from each other.

Abstract: A semiconductor device includes a substrate comprising an antenna and a conductive feature; an integrated circuit (IC) die attached to the substrate and comprising a radio frequency (RF) circuit; and a flexible circuit integrated with the substrate, where the flexible circuit is electrically coupled to the IC die and the substrate, a first portion of the flexible circuit being disposed between opposing sidewalls of the substrate, a second portion of the flexible circuit extending beyond the opposing sidewalls of the substrate, the second portion of the flexible circuit comprising an electrical connector at a distal end.

Abstract: A method for operating a power converter arrangement and a corresponding controller are disclosed. The method includes operating the power converter arrangement in a surge mode, when a DC link voltage of the power converter arrangement reaches a first voltage threshold. The power converter includes a first power converter having an input and an output; a second power converter having an input and an output; and a DC link capacitor circuit coupled to the output of the first power converter and the input of the second power converter and providing the DC link voltage. Operating the power converter arrangement in the surge mode includes: deactivating the second power converter; and operating, at least temporarily, the first power converter in a reverse mode to transfer energy from the DC link capacitor circuit to the input of the first power converter.

Abstract: A method for driving a power transistor includes comparing a measurement signal that is representative of a load current to a comparator threshold that corresponds to an overcurrent threshold; generating a first fault signal when the measurement signal exceeds the comparator threshold for a first time interval; generating a second fault signal when the measurement signal exceeds the comparator threshold for a second time interval that is greater than the first time interval; regulating a control voltage provided to the control terminal of the transistor to turn off the transistor in response to the second fault signal; and in response to the first fault signal, adjusting the control voltage to an adjusted voltage level in order to limit the load current to a reduced current level that is preconfigured to be greater than the overcurrent threshold. The adjusted voltage level is sufficient to maintain the power transistor in an on-state.

Abstract: An ESD protection device may include: a first vertically integrated ESD protection structure comprising a first semiconductor portion, a first contact region disposed on a first side of the first semiconductor portion and a first terminal exposed on a second side of the first semiconductor portion opposite the first side of the first semiconductor portion, a second vertically integrated ESD protection structure comprising a second semiconductor portion, a second contact region disposed on a first side of the second semiconductor portion and a second terminal exposed on a second side of the second semiconductor portion opposite the first side of the second semiconductor portion, an electrical connection layer, wherein the first vertically integrated ESD protection structure and the second vertically integrated ESD protection structure are disposed on the electrical connection layer laterally separated from each other and are electrically connected with each other anti-serially via the electrical connection lay

Abstract: A semiconductor die includes a barrier layer of type III-V semiconductor material, a channel layer of type III-V semiconductor material disposed below the barrier layer, the channel layer forming a heterojunction with the barrier layer such that a two-dimensional charge carrier gas is disposed in the channel layer near the heterojunction, and a capacitor monolithically formed in the semiconductor die, wherein a dielectric medium of the capacitor includes a first section of the barrier layer.

Abstract: A Signal Processing Unit (SPU) having a thresholding circuit configured to detect a peak cell of a radar data cube, and to output an identification of the peak cell and energy values of the peak cell and its adjacent cells; and an interpolation circuit coupled to the thresholding circuit, and configured to determine and transmit from the SPU to a Digital Signal Processor (DSP), a relative position of the peak cell between the adjacent cells based on the energy values.

Abstract: A package is disclosed. In one example, the package comprises a carrier comprising a thermally conductive and electrically insulating layer, a laminate comprising a plurality of connected laminate layers, an electronic component mounted between the carrier and the laminate. An encapsulant is at least partially arranged between the carrier and the laminate and encapsulating at least part of the electronic component.

Abstract: A digital phase-locked loop (DPLL) circuit includes: a first time-to-digital converter (TDC) and a first digital loop filter (DLF) that are configured to be coupled between a reference clock source and a digitally controlled oscillator (DCO), where the first TDC is configured to, during an acquisition mode, generate a phase error by: receiving a reference clock signal from the reference clock source; receiving a clock signal that is based on an output of the DCO divided by a dividing factor, computing a phase error using the reference clock signal and the clock signal; detecting cycle slipping in the computed phase error; and in response to detecting the cycle slipping, modifying the computed phase error to reduce the impact of cycle slipping on the DPLL circuit; and a first frequency divider circuit configured to generate the clock signal by dividing the output of the DCO by the dividing factor.

Abstract: The present disclosure relates to a hybrid multiple-input multiple-output (MIMO) radar concept. Via a first subset of a plurality of transmit channels and during a first time interval, first frequency-modulated continuous-wave (FMCW) radar signals are con-currently transmitted with different phase offsets among different transmit channels of the first subset in accordance with a first predefined code division multiplexing scheme. Via a second subset of the transmit channels and during a second time interval subsequent to the first time interval, second FMCW radar signals are concurrently transmitted with different phase offsets among different transmit channels of the second subset in accordance with a second predefined code division multiplexing scheme.

Abstract: A radar device may include a radar transmitter to output a radio frequency (RF) transmission signal including a plurality of frequency-modulated chirps. The radar device may include a radar receiver to receive an RF radar signal, and generate, based on the RF radar signal, a dataset including a set of digital values, the dataset being associated with a chirp or a sequence of successive chirps. The radar device may include a neural network to filter the dataset to reduce an interfering signal included in the dataset, the neural network being a convolutional neural network. At least one layer of the neural network may be a complex-valued neural network layer includes complex-valued weighting factor, where the complex-valued neural network layer is configured to perform one or more operations according to a complex-valued computation.

Abstract: In an example, a substrate is oriented to a target axis, wherein a residual angular misalignment between the target axis and a preselected crystal channel direction in the substrate is within an angular tolerance interval. Dopant ions are implanted into the substrate using an ion beam that propagates along an ion beam axis. The dopant ions are implanted at implant angles between the ion beam axis and the target axis. The implant angles are within an implant angle range. A channel acceptance width is effective for the preselected crystal channel direction. The implant angle range is greater than 80% of a sum of the channel acceptance width and twofold the angular tolerance interval. The implant angle range is smaller than 500% of the sum of the channel acceptance width and twofold the angular tolerance interval.

Abstract: A memory device comprises a plurality of memory cells and a plurality of evaluation elements, wherein each evaluation element of the plurality of evaluation elements is connectable with a memory cell of the memory device. The memory device further comprises an interconnection unit configured for connecting the plurality of memory cells to a first assignment of evaluation elements in a first state and for connecting the same plurality of memory cells to a second assignment of the evaluation elements in a second state. The memory device comprises an evaluation unit configured for controlling the interconnection unit to transition from the first state to the second state. The evaluation unit is configured for evaluating the plurality of memory cells in the first state to obtain a first evaluation result, and for evaluating the plurality of memory cells in the second state to obtain a second evaluation result.

Abstract: A semiconductor device includes: a semiconductor substrate having opposing first and second main surfaces; a plurality of transistor cells each including a source region, a drift zone, a body region separating the source region from the drift zone, a field plate trench extending into the drift zone and including a field plate, and a planar gate on the first main surface and configured to control current through a channel of the body region; a drain region at the second main surface; and a diffusion barrier structure including alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si. The diffusion barrier structure may be interposed between body regions of adjacent transistor cells and/or extend along the channel of each transistor cell and/or vertically extend in the semiconductor substrate between adjacent field plate trenches.

Abstract: A method for determining a reflectivity value indicating a reflectivity of an object is provided. The method includes performing a Time-of-Flight (ToF) measurement using a ToF sensor. A correlation function of the ToF measurement increases over distance within a measurement range of the ToF sensor such that an output value of the ToF sensor for the ToF measurement is independent of the distance between the ToF sensor and the object. The method further includes determining the reflectivity value based on the output value of the ToF sensor for the ToF measurement.