Abstract: A power connector is provided that is configured to conduct a current and includes a conductive frame including a base structure, an extension structure, and a cap structure that define a current path for the current. The base structure is configured to be coupled to a current supply for receiving the current therefrom. The cap structure is configured to be coupled to an electrical interface of a device to be supplied with the current and outputs the current from the connector to the electrical interface of the device. The extension structure is coupled to and vertically extends between the base structure and the cap structure. The extension structure includes a current constriction region that is configured to cause a defined magnetic field of the current flowing through the current constriction region at a predefined position.

Abstract: Overload detection and protection for power switch circuits. For circuits with faster switching speed, fast fault detection and response to a detected overload condition may be desirable. Detection circuitry may monitor a voltage on the control terminal of one or more power switches. Based on empirical measurements, in an overload condition of a power switch circuit, e.g., a half-bridge circuit, the voltage at the control terminal may increase, and in some examples, increase to a magnitude that is greater than a supply voltage. A comparator may detect a voltage increase that exceeds a voltage magnitude threshold, output an indication to control circuitry for the power switch circuit, and the control circuitry may take action to protect the rest of the circuitry, such as reduce voltage or shut off the power switch circuit.

Abstract: A semiconductor package includes a semiconductor chip, an encapsulation body encapsulating the semiconductor chip, and a metal sheet having a first sheet surface and an opposite second sheet surface. The first sheet surface is exposed at the encapsulation body. The semiconductor chip is arranged at the second sheet surface. The first sheet surface has a pattern having first subdivisions having a first average roughness and second subdivisions having a second average roughness. The first average roughness is greater than the second average roughness.

Abstract: In an embodiment, a semiconductor device includes: a main transistor having a load path; a sense transistor configured to sense a main current flowing in the load path of the main transistor; and a bypass diode structure configured to protect the sense transistor and electrically coupled in parallel with the sense transistor. A sense transistor cell of the sense transistor includes a sense trench and a sense mesa. The sense trench and a bypass diode trench of the bypass diode structure form a common trench. The sense mesa and a bypass diode mesa of the bypass diode structure form a common mesa.

Abstract: According to an embodiment, a security controller is described comprising a memory storing data elements of a data array and a processing circuit configured to determine a power of two such that number of data elements is higher than the power of two but at most equal to double the power of two, determine random first and second integers, change indices of a predefined sequence of indices, comprising performing a first change of the index according to a first permutation if it is lower than the power of two, performing a second change of the index by adding a third integer modulo data array length and performing a third change of the index by a second permutation if it is, following the second change, lower than the power of two, and process the data elements in an order of the changed indices.

Abstract: A gate charge profiler for a power transistor may include a voltage comparator unit and a timer unit. An input signal may control a gate drive current input to a gate of the power transistor to control conduction between a drain and a source of the power transistor. The voltage comparator unit may be configured to compare an input voltage and a threshold voltage, and to output a comparison signal. The input voltage may be a drain-source voltage across the drain and the source of the power transistor or a gate-source voltage across the gate and the source of the power transistor. The timer unit may be configured to output a time value based on input of a transition of the input signal and input of the comparison signal.

Abstract: Systems, methods, and circuitries are disclosed for compressing radar data. In one example, a method includes storing radar data in a memory, the radar data being stored in a data cube having a slow-time dimension, a fast-time dimension, and a channel dimension. The data cube is divided into one or more zones. For each zone a number of data matrices is selected based on a compression factor. Sets of data matrices containing the number of data matrices are formed and, for each set of data matrices, for each data matrix, the data vectors are coded to generate a coded data matrix. A coding for data vectors in a data matrix is the same and a coding for different data matrices is different. The coded data matrices are combined to generate a compressed data matrix for the zone and the compressed data matrices for the one or more zones are stored.

Abstract: A method of forming a semiconductor device includes providing a substrate that comprises a metal region, forming an encapsulant body of electrically insulating material on an upper surface of the metal region, forming an opening in the encapsulant body, and inserting a press-fit connector into the opening, wherein after inserting the press-fit connector into the opening, the press-fit connector is securely retained to the substrate and an interfacing end of the press-fit connector is electrically accessible.

Abstract: A current sensor system includes a magnetic field sensor including a chip plane, a first set of sensor elements sensitive to a first magnetic field component that is aligned in a first direction that is parallel to the chip plane, and a second set of sensor elements sensitive to a second magnetic field component that is aligned in a second direction that is perpendicular to the chip plane; and three conductor structures arranged in parallel to each other and configured to carry a current parallel or antiparallel to a third direction that is perpendicular to the first direction and to the second direction. The three conductor structures generate three magnetic fields based on the current flowing therethrough, where the three magnetic fields produce a first magnetic field distribution of the first magnetic field component and a second magnetic field distribution of the second magnetic field component.

Abstract: A control circuit, a power supply including a control circuit, and a method are disclosed. The control circuit is configured to activate a second output capacitor connected in parallel with a first output capacitor of a power supply when the power supply is in a normal operating mode, and deactivate the second output capacitor when the power supply is in a standby mode.

Abstract: A method of calibrating an analog front end (AFE) filter of a radio frequency integrated circuit (RFIC) includes: making a first measurement of the RFIC at a first measuring frequency while the AFE filter is bypassed; generating a first amplitude estimate and a first phase estimate at the first measuring frequency using the first measurement; making a second measurement of the RFIC at the first measuring frequency while the AFE filter is turned on; generating a second amplitude estimate and a second phase estimate at the first measuring frequency using the second measurement; and calculating a frequency response of the AFE filter at the first measuring frequency, which includes calculating an amplitude response of the AFE filter based on the second amplitude estimate and the first amplitude estimate; and calculating a phase response of the filter based on the first phase estimate and the second phase estimate.

Abstract: A method includes exposing gas sensitive material of a gas sensor device to different adjusted target gas concentrations, determining measurement values of the resistance of the gas sensitive material between first and second contact regions in response to the adjusted target gas concentration, determining a first gas sensor behavior model based on the measurement values of the resistance of the gas sensitive material as a function of the adjusted target gas concentration, translating the first gas sensor behavior model into a corresponding second gas sensor behavior model for the resistance of the gas sensitive material as a function of a control voltage, and sweeping the control voltage based on the second gas sensor behavior model over a control voltage range for providing control voltage dependent resistance data, wherein the control voltage dependent resistance data over the control voltage range form the calibration data for the gas sensor device.

Abstract: A radio frequency (RF) circuit includes an input terminal configured to receive a reception signal from an antenna; an output terminal configured to output a digital output signal; a receive path including a mixer and an analog-to-digital converter (ADC), wherein the receive path is coupled to and between the input and output terminals, wherein the receive path includes an analog portion and a digital portion, and wherein the ADC generates a digital signal based on an analog signal received from the analog portion; a test signal generator configured to generate an analog test signal injected into the analog portion of the receive path; and a digital processor configured to receive a digital test signal from the digital portion, the digital test signal being derived from the analog test signal, analyze a frequency spectrum of the digital test signal, and determine a quality of the digital test signal.

Abstract: A method is described. The method comprises determining a first measurement signal (CS1) which depends on a first load current (I1) through a first transistor (Q1) which is connected in series to a load (Z); determining a second measurement signal (CS2) which depends on a second load current (I2) through a second transistor (Q2) which is connected in series to the load (Z); and comparing the first measurement signal (CS1) and the second measurement signal (CS2), in order to detect the presence of an error.

Abstract: A power electronic assembly includes a board having metal layers laminated onto or between electrically insulating layers, and a laminate inlay embedded in the board. A first metal layer provides electrical contacts at a first side of the board. A second metal layer provides a thermal contact at a second side of the board. A third metal layer is positioned between the first metal layer and the laminate inlay and configured to distribute a load current switched by the laminate inlay. A fourth metal layer is positioned between the second metal layer and the laminate inlay and configured as a primary thermal conduction path for heat generated by the laminate inlay during switching of the load current. A first electrically insulating layer separates the fourth metal layer from the second metal layer so that the fourth metal layer is electrically isolated from but thermally connected to the second metal layer.

Abstract: A transformer includes a winding configured to carry a current. The winding includes a conductor structure through which the current flows and a graphene layer arranged in direct contact with the conductor structure.

Abstract: A current sensor package, comprises a current path and a sensing device. The sensing device is spaced from the current path, and the sensing device is configured for sensing a magnetic field generated by a current flowing through the current path. Further, the sensing device comprises a sensor element. The sensing device is electrically connected to a conductive trace. An encapsulant extends continuously between the current path and the sensing device.

Abstract: Disclosed is a method for producing a semiconductor device, the method including forming a plurality of semiconductor arrangements one above the other, wherein forming each of the plurality of semiconductor arrangements includes forming a semiconductor layer, forming a plurality of trenches in a first surface of the semiconductor layer, and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches. Forming of at least one of the plurality of semiconductor arrangements further includes forming a protective layer covering mesa regions between the plurality of trenches of the respective semiconductor layer, and covering a bottom, the first sidewall and the second sidewall of each of the plurality of trenches that are formed in the respective semiconductor layer.

Abstract: An image projection system includes a first transmitter configured to generate first light beams; a first collimation lens configured to receive the first light beams and generate first collimated light beams to be projected onto an eye to render a first projection image perceived at a first projection plane; a second transmitter configured to generate second light beams; a second collimation lens configured to receive the second light beams and generate second collimated light beams to be projected onto the eye to render a second projection image perceived at a second projection plane; a first beam combiner configured to transmit the first and the second collimated light beams on a combined transmission path; and a scanner configured to steer the first and the second collimated light beams according to a scanning pattern to render the first projection image and the second projection image onto the eye.

Abstract: A method for storing data bits in memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are stored in the memory cells. A method for reading data bits from memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are read from the memory cells based on the coded predefined functionality. Corresponding apparatuses and memories are also disclosed.