Abstract: A power electronics module includes at least one first substrate having on a first side one or more first semiconductor dies, the one or more first semiconductor dies and the at least one first substrate providing a higher power part of the power electronics module, at least one second substrate having on a first side one or more second semiconductor dies, the one or more second semiconductor dies and the at least one second substrate providing a lower power part of the power electronics module, and a common frame at least partially encasing the first and second substrates and being a monobloc part, the higher power part being configured for direct liquid cooling and the lower power part being configured for indirect cooling.

Abstract: A system and method are provided for generating Unique Digital Signatures (UDS) for semiconductor memories to improve data security. Generally, the method involves allocating a number of native memory cells in a memory device; obtaining a multibit binary entropy string (BES) using variations of threshold voltages (VT) of the allocated cells as an entropy source; and mathematically manipulating the BES to generate the UDS. Optionally, the BES can be concatenated with another multibit binary number from a second entropy source internal or external to the memory device, and the result of the concatenation mathematically manipulated to generate the UDS. In one embodiment, a reference voltage is located at a median VT for the cells, and the BES is obtained by reading the cells versus the reference, assigning those having a VT above the reference a first bit value, and the remaining cells a second bit value.

Abstract: A molded semiconductor package includes: a semiconductor die embedded in a mold compound; a first heat spreader partly embedded in the mold compound and thermally coupled to a first side of the semiconductor die; and a second heat spreader partly embedded in the mold compound and thermally coupled to a second side of the semiconductor die opposite the first side. The first heat spreader includes at least one heat dissipative structure protruding from a side of the first heat spreader uncovered by the mold compound and facing away from the semiconductor die. The mold compound is configured to channel a fluid over the at least one heat dissipative structure in a direction parallel to the first side of the power semiconductor die. Corresponding methods of production and electronic assemblies are also described.

Abstract: An infrared emitter with a glass lid for emitting infrared radiation comprises a package enclosing a cavity, wherein a first part is transparent for infrared radiation and a second part comprises a glass material and a heating structure configured for emitting the infrared radiation, wherein the heating structure is arranged in the cavity between the first part and the second part of the package.

Abstract: An apparatus includes a controller a current mode controller that produces an output voltage by supplying output current from at least one power supply phase of a power supply to power a load. The controller produces an error current signal based on a difference between a magnitude of the output current supplied from the power supply to a load and a phase current setpoint. Based on a magnitude of the error current signal, control a pulse width setting of a pulse width modulation signal controlling the at least one power supply phase. The controller varies a leading edge and a falling edge of a pulse width ON-time of the pulse width modulation signal over each of multiple control cycles depending on variations in the magnitude of the pulse width setting.

Abstract: A method includes providing a semiconductor body including a plurality of two-dimensional charge carrier gas channels, forming a gate fin by forming a pair of gate trenches in an upper surface of the semiconductor body, the pair of gate trenches exposing each one of two-dimensional charge carrier gas channels, providing source and drain contacts that are electrically connected to each one of the plurality of two-dimensional charge carrier gas channels, providing a gate structure that is configured to control a conductive connection between the source and drain contacts, wherein providing the gate structure includes forming a layer of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and forming a conductive gate electrode on top of the layer of doped type III-nitride semiconductor material.

Abstract: In accordance with an embodiment, a circuit includes: a first super source follower; a compensation circuit having a compensating node configured to provide a voltage of opposite phase of a voltage of an internal node of the first super source follower; and a first compensation capacitor coupled between an input of the first super source follower and the compensating node of the compensation circuit.

Abstract: A capacitive sensor includes a first electrode structure; a second electrode structure that is counter to the first electrode structure, wherein the second electrode structure is movable relative to the first electrode structure and is capacitively coupled to the first electrode structure to form a capacitor having a capacitance that changes with a change in a distance between the first electrode structure and second electrode structure; a signal generator configured to apply an electrical signal at an input or at an output of the capacitor to induce a voltage transient response at the output of capacitor; and a diagnostic circuit configured to detect a fault in the capacitive sensor by measuring a time constant of the first voltage transient response and detecting the fault based on the time constant and based on whether the first electrical signal is the pull-in signal or the non-pull-in signal.

Abstract: A semiconductor device includes: a silicon carbide semiconductor body having a source region of a first conductivity type and a body region of a second conductivity type; and a trench structure extending from a first surface into the silicon carbide semiconductor body along a vertical direction, the trench structure having a gate electrode and a gate dielectric. The trench structure is stripe-shaped and runs along a longitudinal direction that is perpendicular to the vertical direction. The source region includes a first source sub-region and a second source sub-region alternately arranged along the longitudinal direction. A doping concentration profile of the first source sub-region along the vertical direction differs from a doping concentration profile of the second source sub-region along the vertical direction. A corresponding method of manufacturing the semiconductor device is also described.

Abstract: In an embodiment, a Group III nitride-based transistor device includes a source electrode, a drain electrode and a gate electrode positioned on a first major surface of a Group III nitride based-based layer, wherein the gate electrode is laterally arranged between the source electrode and the drain electrode, a passivation layer arranged on the first major surface and a field plate coupled to the source electrode, the field plate having a lower surface arranged on the passivation layer. The field plate is laterally arranged between and laterally spaced apart from the gate electrode and the drain electrode.

Abstract: A method and a transistor device are disclosed. The transistor device includes: a semiconductor body; first regions of a first doping type and second regions of a second doping type in an inner region and an edge region of the semiconductor body; transistor cells in the inner region of the semiconductor body, each transistor cell including a body region and a source region, the transistor cells including a common drain region; and a buffer region arranged between the drain region and the first and second regions. A dopant dose in the first and second regions decreases towards an edge surface of the semiconductor body. A dopant dose in the buffer region decreases towards the edge surface.

Abstract: In a method for manufacturing an electrostatic discharge protection circuit, an electrostatic discharge device structure is formed during a front side processing of a semiconductor substrate in a first area. Contact pads are formed on the front side on the electrostatic discharge device structure and in a second area. During back side processing of the semiconductor substrate, a metal connection between the first electrostatic discharge device structure and the second area is formed.

Abstract: A method is disclosed. In one example, the method includes bonding a first panel of a first material to a base panel in a first gas atmosphere, wherein multiple hermetically sealed first cavities encapsulating gas of the first gas atmosphere are formed between the first panel and the base panel. The method further includes bonding a second panel of a second material to at least one of the base panel and the first panel, wherein multiple second cavities are formed between the second panel and the at least one of the base panel and the first panel.

Abstract: A method includes detecting a voltage at a configuration terminal of a mobile industry processor interface (MIPI) radio frequency front end (RFFE) device with a timing based on a MIPI RFFE signal received by the MIPI RFFE device, and setting an address for the MIPI RFFE device based on the detected voltage.

Abstract: A circuit is provided that comprises a transformer having a first coil, which is arranged on a substrate, a second coil, which is arranged above the first coil on the substrate, and a dielectric between the first coil and the second coil. The circuit furthermore comprises a resonant circuit, which is couplable to the first coil and/or the second coil to form a resonant loop, wherein a measure of a characteristic frequency of the resonant loop and/or a measure of a power consumption of the resonant loop is able to be tapped off at an output of the resonant circuit. A corresponding method is also provided.

Abstract: In accordance with an embodiment, a gas-sensitive device includes a substrate structure, and a gas sensitive capacitor. The gas sensitive capacitor a first capacitor electrode in form of a gas-sensitive layer on a first main surface region of an insulation layer, and a second capacitor electrode in form of a buried conductive region below the insulation layer, so that the insulation layer is arranged between the first and second capacitor electrode. The gas-sensitive layer comprises a sheet impedance which changes in response to the adsorption or desorption of gas molecules.

Abstract: A gate driver system includes a transistor configured to be driven between switching states, the transistor including a control terminal controlled by a control voltage that has a maximum rated limit; and a gate driver coupled to the control terminal by a turn-on current path, the gate driver being configured to control the control voltage in order to drive the transistor between the switching states. The turn-on current path includes a resistor and a Zener diode connected in series, with an anode of the Zener diode connected to the control terminal and a cathode of the Zener diode connected to the resistor. The turn-on current path is configured to provide an on-current to increase the control voltage above a switching threshold. While the transistor is turned on, the Zener diode is configured to limit the control voltage to a voltage level limit that is less than the maximum rated limit.

Abstract: A semiconductor includes a carrier; a semiconductor element arranged on the carrier; a first row of terminals arranged along a first side face of the carrier; a second row of terminals arranged along a second side face of the carrier opposite the first side face; and an encapsulation body encapsulating the semiconductor element, wherein the semiconductor element comprises a first transistor structure and a second transistor structure, wherein the first row of terminals comprises a first gate terminal, a first sensing terminal coupled, and a first power terminal, wherein the second row of terminals, a second sensing terminal, and a second power terminal.

Abstract: A gate driver device includes a first field effect transistor and a first driver circuit. The first field effect transistor includes a first gate electrode and a first backgate structure. The first driver circuit supplies a first backgate drive signal to the first backgate structure.

Abstract: A semiconductor device includes type IV semiconductor base substrate, first and second device areas that are electrically isolated from one another, a first region of type III-V semiconductor material formed over the first device area, a second region of type III-V semiconductor material formed over the second device area, the second region of type III-V semiconductor material being laterally electrically insulated from the first region of type III-V semiconductor material, a first high-electron mobility transistor integrally formed in the first region, and a second high-electron mobility transistor integrally formed in the second region. The first and second high-electron mobility transistors are connected in series. A source terminal of the first high-electron mobility transistor is electrically connected to the first device area. The first device area is electrically isolated from a subjacent intrinsically doped region of the base substrate by a first two-way voltage blocking device.