Abstract: A substrate includes a dielectric insulation layer, a first metallization layer arranged on a first surface of the dielectric insulation layer, and a second metallization layer arranged on a second, opposite surface of the dielectric insulation layer. The dielectric insulation layer includes an outer edge extending between the first and second surfaces. The outer edge includes first sections and second sections. Along each first section, a difference between a first distance and a second distance has a first value. Along each second section, the difference between the first and second distances has a second value that is different from the first value. The first distance is a distance between the outer edge of the dielectric insulation layer and an outer edge of the first metallization layer. The second distance is a distance between the outer edge of the dielectric insulation layer and an outer edge of the second metallization layer.

Abstract: A power semiconductor module arrangement includes: a housing having a plurality of through holes; a substrate forming a ground surface of the housing; and a plurality of terminal elements mechanically and electrically connected to the substrate. A first end of each terminal element is arranged inside the housing and connected to the substrate. Each terminal element extends from the substrate in a vertical direction perpendicular to a top surface of the substrate through one of the through holes to the outside of the housing, such that a second end of each terminal element is arranged outside of the housing. Each terminal element includes a holding element arranged between the first end and the second end. Each holding element exerts a force on the housing, thereby holding the housing in a desired position with regard to the substrate.

Abstract: Substrates for use with semiconductor devices are provided. The substrates include a barcode laser etched into a metallic surface or layer of the substrate. A wall of non-metallic material may be formed on the metallic surface or layer and frame the barcode. Separately or in combination, an optically transparent encapsulant may cover a region of the metallic surface or layer that includes the barcode, where the optically transparent encapsulant reduces oxidation of metallic debris produced by laser etching of the barcode and that remains on or near the barcode. Separately or in combination, the substrate may include an electrically insulative body covered by the metallic layer and a trench formed in the metallic layer along a perimeter of the barcode and that exposes the electrically insulative body. Methods of improving readability of the barcode are also provided.

Abstract: Systems, methods, and devices are provided for controlling processing of ultra-wideband (UWB) secure training sequence (STS) signals based on previously received UWB STS signals. In one example, a controller device is configured to receive data derived from at least one secure training sequence (STS) confidence level figure of merit (STS CLFOM data), wherein the STS CLFOM data is based on a correlation between a UWB signal received by a first UWB receiver device and a reference STS template; and control processing of subsequently received UWB signals based on the data.

Abstract: An image processing system, includes an image sensor, a bus structure coupled to the image sensor, and a system memory coupled to the image sensor via the bus structure. A direct memory access (DMA) controller is coupled to the bus structure. The DMA controller includes in-line logic hardware configured to retrieve raw pixel data from the image sensor, and internally process the retrieved raw pixel data thereby providing processed pixel data.

Abstract: A semiconductor device module includes an application board, a plurality of semiconductor device packages disposed on the application board, each one of the semiconductor device packages including a semiconductor die, a leadframe including a plurality of leads, the leads including a spring support and a heat dissipation element, and an encapsulant embedding the semiconductor die and first portions of the leads, an external heatsink, and one or more thermally conductive interface layers disposed between the semiconductor device package and the heatsink.

Abstract: A power module includes: a first substrate comprising a patterned first metallization; a second substrate comprising a patterned second metallization that faces the patterned first metallization; a first plurality of vertical power transistor dies having a drain pad attached to a first part of the patterned first metallization and a source pad electrically connected to a first part of the patterned second metallization; a second plurality of vertical power transistor dies having a drain pad attached to a second part of the patterned first metallization and a source pad electrically connected to a second part of the patterned second metallization; and a multi-level lead frame between the first substrate and the second substrate and attached to each of the first part of the patterned first metallization, the first part of the patterned second metallization, the second part of the patterned first metallization, and the second part of the patterned second metallization.

Abstract: In some examples, this disclosure describes a method of operating a plurality of battery management circuits of a battery management system associated with an electric device. The method may comprise adjusting a first trim value associated with a first battery management circuit during operation of the electric device, and adjusting a second trim value associated with a second battery management circuit during operation of the electric device. The method may also comprise sinking a first amount of current in the first battery management circuit based on the first trim value; and sinking a second amount of current in the second battery management circuit based on the second trim value, wherein sinking the first amount of current and sinking the second amount of current causes the first battery management circuit and the second battery management circuit to consume substantially similar amounts of current.

Abstract: A power transistor device includes a semiconductor substrate, a gate trench extending into the semiconductor substrate, a transistor gate provided in the gate trench, and an insulating structure formed between the transistor gate and a side wall of the gate trench. The insulating structure is configured to electrically insulate the transistor gate from a channel region which extends along the side wall of the gate trench. The insulating structure includes a layer of piezoelectric material.

Abstract: A silicon carbide device includes a silicon carbide substrate, a contact layer located on the silicon carbide substrate and including nickel and silicon, a barrier layer structure including titanium and tungsten, and a metallization layer comprising copper, wherein the contact layer is located between the silicon carbide substrate and at least a part of the barrier layer structure, wherein the barrier layer structure is located between the silicon carbide substrate and the metallization layer, wherein the metallization layer is configured as a contact pad of the silicon carbide device.

Abstract: A semiconductor module includes a power electronics carrier including a metallization layer disposed on an electrically insulating substrate, a power semiconductor die mounted on the power electronics carrier, a housing that surrounds an interior volume over the power electronics carrier, an electrically insulating encapsulant within the interior volume that encapsulates the power semiconductor die, wherein the electrically insulating encapsulant is configured to transform during operation of the power semiconductor die such that a liquified envelope of the electrically insulating encapsulant surrounds the power semiconductor die and such that a solid outer region of the electrically insulating encapsulant surrounds the liquified envelope.

Abstract: A digital microphone includes a logarithmic amplifier; an analog-to-digital converter (ADC) coupled to the logarithmic amplifier; a digital decompression component coupled to the ADC; and a digital filter coupled to the digital decompression component, wherein the digital filter includes a controlled upsampling component coupled to an input of the digital filter and a controlled downsampling component coupled to an output of the digital filter.

Abstract: The present disclosure generally relates to a method of manufacturing a contact on a silicon carbide semiconductor substrate wherein the method comprises providing a 4H—SiC semiconductor substrate, irradiating a surface area of the 4H—SiC semiconductor substrate with a first thermal annealing laser beam, thereby generating a phase separation of the surface area comprising at least a 3C—SiC layer, and depositing a contact material onto the 3C—SiC layer to form a contact layer on the semiconductor substrate. The disclosure further relates to a silicon carbide semiconductor device with an Ohmic contact comprising a 4H—SiC semiconductor substrate, a 3C—SiC layer, and a contact layer directly in contact with the 3C—SiC layer at the semiconductor surface.

Abstract: In accordance with an embodiment, an RF amplifier includes: a first amplifier including a first transistor coupled to a first supply node configured to provide a first supply voltage, the first transistor having a first device periphery; a second amplifier including a second transistor coupled to a second supply node configured to provide a second supply voltage higher than the first supply voltage, the second transistor having a second device periphery; and a combining network coupled to an output of the first amplifier, an output of the second amplifier, and an RF output port. The first device periphery, the first supply voltage, the second device periphery, and the second supply voltage are configured to maintain a junction temperature ratio of between 0.3 and 1.0, and the junction temperature ratio is a ratio of a temperature of the first amplifier to a temperature of the second amplifier.

Abstract: An electronic system is disclosed. In one example, the electronic system comprises an at least partially electrically conductive carrier, an electronic component, and an intermetallic connection structure connecting the carrier and the component. The intermetallic connection structure comprising an intermetallic mesh structure in a central portion of the intermetallic connection structure, and opposing exterior structures without intermetallic mesh and each arranged between the intermetallic mesh structure and the carrier or the component.

Abstract: A silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) and a method for forming a SiC MOSFET are disclosed. In an example, the method includes forming a gate dielectric that adjoins a body region arranged in a semiconductor body, and forming a gate electrode on the gate dielectric. Forming the gate electrode includes forming a first electrode layer, implanting work function adjusting atoms into the first electrode layer, and forming a second electrode layer on the first electrode layer.

Abstract: A package is disclosed. In one example, the package includes an electronic component and an encapsulant encapsulating at least part of the electronic component. A first electrically conductive structure is arranged on one side of the electronic component, a second electrically conductive structure arranged on an opposing other side of the electronic component and being electrically coupled with the electronic component, and at least one sidewall recess at the encapsulant. The first electrically conductive structure and the second electrically conductive structure are configured to be at different electric potentials during operation of the package. The first electrically conductive structure and the second electrically conductive structure are exposed at opposing main surfaces of the encapsulant.

Abstract: In an embodiment, a semiconductor device is provided. The semiconductor device may include a semiconductor body including a first doped region of a first conductivity type and a second doped region of a second conductivity type. The semiconductor device may include a metal structure, in the semiconductor body, overlying the second doped region. The metal structure may include a first sidewall adjacent a first portion of the first doped region, a second sidewall adjacent a second portion of the first doped region, and a third sidewall adjacent the second doped region. The semiconductor device may include a Schottky contact including a junction of the third sidewall of the metal structure with the second doped region.

Abstract: A hardware (HW) accelerator architecture is described that adapts to a number of post-quantum cryptography (PQC) algorithms. The architecture determines whether to re-provision memory that stores constants values for arithmetic computations used for executed PQC algorithms. The architecture enables only a single set of constants to be stored at any particular time and the memory only needs to have a capacity to ensure that the largest set of constants among one of several PQC algorithms is stored while obviating the need to store the constants used across all PQC algorithms.

Abstract: A method of manufacturing a semiconductor device is described. The method includes providing a semiconductor substrate. The semiconductor substrate includes a high-doped semiconductor substrate layer, a high-doped semiconductor device layer, and a low-doped semiconductor etch stop layer arranged between the high-doped semiconductor substrate layer and the high-doped semiconductor device layer. The high-doped semiconductor substrate layer is removed, wherein the removing includes dopant selective chemical etching stopping at the low-doped semiconductor etch stop layer. Further, the low-doped semiconductor etch stop layer is thinned to generate an exposed surface of the high-doped semiconductor device layer.