Abstract: The present disclosure relates to the technical field of semiconductors. Disclosed is a multi-layer semiconductor material structure and a preparation method thereof, solving the problems of the existing semiconductor materials that have poor heat dissipation, high cost, and cannot be mass-produced. The multi-layer semiconductor material structure includes a highly thermally conductive support substrate and a crystallized device function layer, where the device function layer is provided on the highly thermally conductive support substrate, and has a single-crystal surface layer.

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the same thereof, and an electronic apparatus including the semiconductor device. According to embodiments of the present disclosure, the semiconductor device includes a channel portion, source/drain portions connected to the channel portion on two opposite sides of the channel portion, and a gate stack intersecting with the channel portion. The channel portion includes a first portion extending in a vertical direction with respect to a substrate and a second portion extending from the first portion to two opposite sides in a lateral direction with respect to the substrate, respectively.

Abstract: A complementary storage unit and a method of preparing the same, and a complementary memory. The complementary storage unit includes: a control transistor, a pull-up diode and a pull-down diode. The control transistor is configured to control reading and writing of the storage unit. One end of the pull-up diode is connected to a positive selection line, and the other end thereof is connected to a source end of the control transistor, so as to control a high-level input. One end of the pull-down diode is connected to a negative selection line, and the other end thereof is connected to the source end of the control transistor, so as to control a low-level input. The pull-up diode and the pull-down diode are symmetrically arranged in a first direction.

Abstract: The memory cell includes: a piezoelectric substrate layer, wherein two ends of the piezoelectric substrate layer are respectively provided with a first electrode and a second electrode, and a current-free drive of skyrmion is implemented by applying a voltage to the first electrode and the second electrode; a magnetic layer on a surface of the piezoelectric substrate layer, wherein the magnetic layer is used to form a heterojunction with the piezoelectric substrate layer, and is used to generate, stabilize, and serve as a basic carrier for a movement of the skyrmion; wherein the magnetic layer includes a convex body, the convex body is configured to divide the magnetic layer into a bit region and a memory region, and the bit region is provided with a magnetic tunnel junction used to perform generation and detection functions of the skyrmion.

Abstract: A semiconductor device and a method of manufacturing the same, and an electronic apparatus including the semiconductor device are provided. The semiconductor device includes: an active region, on a substrate, extending substantially in a vertical direction; a gate stack formed around at least a part of a periphery of the active region, the active region including a channel region opposite to the gate stack, and a first source/drain region and a second source/drain region, and the gate stack including a gate dielectric layer, a work function tuning layer and a gate electrode material layer, and the work function tuning layer being between the gate electrode material layer and the channel region; and a first low-k dielectric layer extending from a first end of the work function tuning layer to surround a first corner of an end portion, on a side facing the channel region, of the gate electrode material layer.

Abstract: A method for manufacturing a semiconductor device. A photolithographic coating, including a first film, a photolithographic film, and a second film, is formed on the to-be-connected structure. Refractive indexes of the first film and the second film are smaller than 1. The photolithographic coating is exposed to a light having a first wavelength, to image the to-be-connected structure to a first region of the photolithographic film. The photolithographic coating is exposed to a light having a second wavelength through a mask, to image the mask to a second region of the photolithographic film. A region in which the first region and the second region overlap serves as a connection region corresponding to the to-be-connected structure, and thereby self-alignment between a layer of the to-be-connected structure and a layer where a contact hole is arranged is implemented.

Abstract: A method for manufacturing a semiconductor device. A photolithographic coating, including a first film, a photolithographic film, and a second film, is formed on the to-be-connected structure. Refractive indexes of the first film and the second film are smaller than 1, so that the photolithographic coating forms an optical structure with a high reflection coefficient. The photolithographic coating is exposed to a light having a target wavelength through a mask. The to-be-connected structure is reflected in the photolithographic coating, and hence serves as another mask and is imaged to the photolithographic film. A pattern of the mask is simultaneously imaged to the photolithographic film. That is, both the to-be-connected structure and the pattern of the mask are imaged to a target region of the photolithographic film, and the target region corresponds to the to-be-connected structure.

Abstract: An interconnection structure for semiconductor devices formed on a substrate may be arranged under the semiconductor devices. The interconnection structure includes at least one via layer and at least one interconnection layer alternately arranged in a direction from the semiconductor device to the substrate, wherein each via layer includes via holes respectively arranged under at least a part of the semiconductor devices, and each interconnection layer includes conductive nodes respectively arranged under at least a part of the semiconductor devices, and in a same interconnection layer, a conductive channel is provided between at least one conductive node and at least another node; and the via holes in each via layer and the conductive nodes in each interconnection layer corresponding to the via holes at least partially overlap with each other in the direction from the semiconductor device to the substrate.

Abstract: Provided are a self-aligned nanometer through-silicon-via structure and a method of preparing the same. According to the preset range and positions of the first and second trenches, the second preset pattern is formed, and then the first initial blind hole is formed by etching based on the second preset pattern, so that the position of the nanometer through-silicon-via is determined. The depth of the buried power rail may be determined by etching the silicon substrate with the first preset depth, and the depth of the self-aligned nanometer through-silicon-via may be determined by etching the silicon substrate with the second preset depth or thinning the fourth structure from a side of the silicon substrate.

Abstract: Provided are a nanowire/nanosheet device with a support portion, a method of manufacturing the same, and an electronic apparatus including the nanowire/nanosheet device.

Abstract: A storage unit, a method of manufacturing the storage unit, and a three-dimensional memory. The storage unit includes: a first conductivity-type substrate; a channel layer stacked on the first conductivity-type substrate in a first direction; a second conductivity-type conduction layer including a first part and a second part that are connected, the first part being located between the first conductivity-type substrate and the channel layer, and the second part being formed in a via hole passing through the channel layer; a channel passage layer penetrating the channel layer and the first part in a negative direction of the first direction, and extending into an interior of the first conductivity-type substrate; and an insulating layer located in the channel layer and surrounding a periphery of the channel passage layer. The first conductivity-type substrate and the second conductivity-type conduction layer provide carriers required for reading and erasing operations, respectively.

Abstract: Provided is an L-shaped stepped word line structure including: L-shaped word line units, each including a long side extending in a second direction and arranged adjacent to a gate line slit, and a short side extending in a first direction. A word line terminal included in the short side is formed in a stepped stacked layer structure including stacked layer pairs formed of an insulating material, a region close to the gate line slit in a stacked layer of each stacked layer pair serves as a replacement metal region including a short side region surface/internal metal layer respectively located on a surface/in an interior. In a first direction, a length of the short side region surface metal layer is greater than that of the short side region internal metal layer, and the word line terminal corresponds to the short side region surface metal layer.

Abstract: The vertical MOSFET device includes: an active region including a first source/drain layer, a channel layer and a second source/drain layer vertically stacked on a substrate in sequence, wherein an outer periphery of the channel layer is recessed with respect to outer peripheries of the first source/drain layer and the second source/drain layer; a spacing layer including an upper spacing layer and a lower spacing layer, wherein the upper spacing layer and the lower spacing layer are both in contact with a side surface of the channel layer and are not in communication with each other; and a gate stack formed at least on a lateral outer periphery of the channel layer and embedded in a groove space between the upper spacing layer and the lower spacing layer.

Abstract: Disclosed are a semiconductor device, a method for manufacturing the same, an integrated circuit, and an electronic apparatus. The semiconductor device includes: a substrate; an active region on the substrate, the active region includes a first source and drain layer, a channel layer, and a second source and drain layer sequentially stacked on the substrate; a gate stack formed around an outer periphery of the channel layer; and an intermediate dielectric layer and a second conductive layer around an outer periphery of the gate stack and an outer periphery of the active region. The device and method provided by the present disclosure are used to solve the technical problem that the performances of the vertical device in the related art need to be improved. A semiconductor device with better performances is provided.

Abstract: The method includes: reading a memory cell having a encoded information bit, so as to obtain an LLR value of a current memory cell with reference to a pre-established LLR table according to a storage time, a threshold voltage partition and a comprehensive distribution corresponding to the current memory cell during reading; and performing a soft decoding operation on a codeword in the memory cell having the encoded information bit according to the read LLR value of the current memory cell, wherein the comprehensive distribution of the current memory cell is determined according to an influence of a memory cell adjacent to the current memory cell on a distribution of the current memory cell; an input of the pre-established LLR table comprises a storage time, a threshold voltage partition and a comprehensive distribution, and an output of the pre-established LLR table comprises an LLR value.

Abstract: A memory device and a method for manufacturing the same, and an electronic apparatus including the memory device are provided. The memory device may include: a substrate (1001); an electrode structure on the substrate (1001), in which the electrode structure includes a plurality of first electrode layers and a plurality of second electrode layers that are alternately stacked; a plurality of vertical active regions penetrating the electrode structure; a first gate dielectric layer and a second gate dielectric layer, in which the first gate dielectric layer is between the vertical active region and each first electrode layer of the electrode structure, and the second gate dielectric layer is between the vertical active region and each second electrode layer of the electrode structure, each of the first gate dielectric layer and the second gate dielectric layer constitutes a data memory structure.

Abstract: Provided is a method for optimizing a lithography quality, including: determining a wave function stray term introduced by a surface roughness of a metal film layer based on Eigen matrix method and Bloch theorem; inputting the wave function stray term into a lithography quality deviation mathematical model for calculation and simulation to obtain an influence analysis curve of a roughness of the metal film layer on a lithography quality, the influence analysis curve characterizes an influence result of the roughness of the metal film layer on the lithography quality; reducing the surface roughness of the metal film layer and/or providing a metal-dielectric multilayer film structure between a mask above a metal-dielectric unit and air according to the influence result, so as to optimize the lithography quality of the metal-dielectric unit. Provided is an apparatus for optimizing a lithography quality, an electronic device, a computer-readable storage medium and computer program product.

Abstract: Provided is an all-electrically-controlled spintronic neuron device, a neuron circuit and a neural network. The neuron device includes: a bottom antiferromagnetic pinning layer; a synthetic antiferromagnetic layer formed on the bottom antiferromagnetic pinning layer; a potential barrier layer formed on the ferromagnetic free layer, wherein a region of the ferromagnetic free layer directly opposite to the potential barrier layer forms a threshold region; a ferromagnetic reference layer formed on the potential barrier layer; wherein the potential barrier layer, the ferromagnetic reference layer and the ferromagnetic free layer form a magnetic tunnel junction; a first antiferromagnetic pinning layer and a second antiferromagnetic pinning layer formed on an exposed region of the ferromagnetic free layer except the region directly opposite the potential barrier layer, and located on two sides of the potential barrier layer; and a first electrode formed on the ferromagnetic reference layer.

Abstract: Provided are a three-dimensional vertical single transistor ferroelectric memory and a manufacturing method thereof. The ferroelectric memory comprises: a substrate; an insulating dielectric layer provided at the substrate; a channel structure extending through the insulating dielectric layer and connected to the substrate, the channel structure having a source/drain region and a channel region connected to the source/drain region; and a gate stack structure arranged around the channel structure and provided in the insulating dielectric layer opposite to the channel region, the gate stack structure comprising a ferroelectric insulation layer and a gate sequentially stacked in a direction away from the channel structure. The ferroelectric memory having the above structure can replace conventional DRAMs. Therefore, the invention realizes a high intensity high speed memory.

Abstract: An embodiment of the present disclosure provides an etching method, having the following steps: forming a modified layer having a thickness of one or several atom layers on a selected region of a surface of a semiconductor material layer by using a modifier; and removing the modified layer. When a semiconductor is processed, this method achieves precise control over the etching thickness and improves the etching rate at the same time.