Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof, and an electronic device including the semiconductor device. The semiconductor device may include: a substrate; a first source/drain region, a channel region and a second source/drain region stacked sequentially on the substrate and adjacent to each other, and a gate stack formed around an outer periphery of the channel region; wherein the gate stack has a thickness varying in a direction perpendicular to a top surface of the substrate.

Abstract: An interconnection structure and a method of manufacturing the same, and an electronic device including the interconnection structure are provided.

Abstract: A data readout circuit of a RRAM includes: an adaptive current sense amplifier (CSA) and a reference current generator, the adaptive CSA is configured to electrically connect to the RRAM, and the adaptive CSA is electrically connected to the reference current generator; the reference current generator is configured to generate a basic reference current; the adaptive CSA is configured to obtain a reference current according to the basic reference current and a bit-line current of the RRAM; and the adaptive CSA is configured to compare the size of the reference current and that of the bit-line current so as to read out stored data. The present disclosure can improve the problem of data readout error due to the degradation of high resistance state of the RRAM.

Abstract: A writing method and erasing method of a fusion memory are provided, and the fusion memory includes a plurality of memory cells, and each memory cell of the plurality of memory cells includes a bulk substrate; a source and a drain on the bulk substrate, a channel region extending between the source and the drain, and a ferroelectric layer and a gate stacked on the channel region; and the writing method includes: applying a first voltage between the gate of at least one memory cell and the bulk of at least one memory cell, in which the first voltage is less than a reversal voltage at which the ferroelectric layer is polarization reversed, and each of the source and the drain is grounded or in a floating state.

Abstract: The present disclosure provides a method for optimizing mask parameters, and the method includes: acquiring a test pattern, light source parameters, and initial mask parameters, the initial mask parameters including a mask thickness and an initial mask sidewall angle; generating multiple sets of candidate mask parameters according to the initial mask sidewall angle in the initial mask parameters; the multiple sets of candidate mask parameters including different mask sidewall angles and the same mask thickness; obtaining an imaging contrast of each set of candidate mask parameters based on the test pattern and the light source parameters; and selecting an optimal mask sidewall angle from the multiple sets of candidate mask parameters according to the imaging contrasts.

Abstract: The present disclosure discloses a data readout circuit of a RRAM and a RRAM circuit. The data readout circuit of the RRAM comprises: an adaptive current sense amplifier (CSA) and a reference current generator, the adaptive CSA is configured to electrically connect to the RRAM, and the adaptive CSA is electrically connected to the reference current generator; the reference current generator is configured to generate a basic reference current; the adaptive CSA is configured to obtain a reference current according to the basic reference current and a bit-line current of the RRAM; and the adaptive CSA is configured to compare the size of the reference current and that of the bit-line current so as to read out stored data. The present disclosure can improve the problem of data readout error due to the degradation of high resistance state of the RRAM.

Abstract: The present invention relates to a semiconductor memory cell structure, a semiconductor memory as well as preparation method and application thereof. The semiconductor memory cell structure includes: a substrate; and a first transistor layer, an isolation layer and a second transistor layer. The first transistor layer includes a first stack structure formed by stacking a first source, a first channel, and a first drain from bottom to top; and a first gate located on a sidewall of the first stack structure. The second transistor layer includes: a second stack structure formed by stacking a second drain, a second channel, and a second source from bottom to top; and a second gate located on a sidewall of the second stack structure, at least a part of a sidewall of the second drain is in direct contact with the first gate.

Abstract: The present disclosure relates to a vertical MOSFET device, a manufacturing method and application thereof.

Abstract: A semiconductor device with a sidewall interconnection structure and a method for manufacturing the same, and an electronic apparatus including the semiconductor device are provided. According to embodiments, the semiconductor device includes: a vertical stack including a plurality of element layers, wherein each element layer of the plurality of element layers includes a plurality of semiconductor elements and a metallization layer for the plurality of semiconductor elements; and an interconnection structure laterally adjoined the vertical stack. The interconnection structure includes: an electrical isolation layer; and a conductive structure in the electrical isolation layer, wherein at least a part of a conductive structure in the metallization layer of the each element layer is in contact with and electrically connected to the conductive structure at a corresponding height in the interconnection structure in a lateral direction.

Abstract: A method of manufacturing a parallel structure of semiconductor devices includes: disposing a semiconductor stack, which includes source/drain layers disposed vertically in sequence and channel layers therebetween, on a substrate; patterning the semiconductor stack into a predetermined shape to define an active region; forming gate stacks around at least part of peripheries of the channel layers; forming an isolation layer on peripheries of the active region and the gate stack; forming first to third conductive channels on a sidewall of the isolation layer; determining the pre-determined shape and a shape of the gate stacks, such that one of the source/drain layers on two sides of the channel layer passes through the isolation layer to contact the first conductive channel, while the other one passes through the isolation layer to contact the second conductive channel, and the gate stack passes through the isolation layer to contact the third conductive channel.

Abstract: The present disclosure provides a storage unit, a data writing method and a data reading method thereof, a memory and an electronic device. The storage unit includes a semiconductor substrate, a first insulating medium layer, a ferroelectric thin film layer, a bottom electrode, a tunnel junction, a first metal interconnection portion, a second metal interconnection portion, a third metal interconnection portion and a fourth metal interconnection portion. The first insulating medium layer is formed on the semiconductor substrate, the ferroelectric thin film layer is disposed on the first insulating medium layer, the bottom electrode is formed on the ferroelectric thin film layer, and the tunnel junction is formed on the bottom electrode. The first metal interconnection portion is connected to a first end of the bottom electrode, and the third metal interconnection portion is connected to a second end of the bottom electrode.

Abstract: A semiconductor apparatus with a heat dissipation conduit in a sidewall interconnection structure, a method of manufacturing the semiconductor apparatus, and an electronic device including the semiconductor apparatus. According to the embodiments, the semiconductor apparatus includes: a carrier substrate having a first region and a second region adjacent to each other; a semiconductor device on the first region; and an interconnection structure on the second region, wherein the interconnection structure includes: an electrical isolation layer; a conductive structure in the electrical isolation layer, wherein at least a part of components require to be electrically connected in the semiconductor device is in contact with and therefore electrically connected to the conductive structure in a lateral direction, wherein the conductive structure is located at a corresponding height in the interconnection structure; and a heat dissipation conduit in the electrical isolation layer.

Abstract: A signal processing method is applied to an RFID electronic tag, and includes: coding a digital baseband signal to obtain a coded signal; performing phase-shift keying modulation on the coded signal to obtain a first modulated signal; performing OFDM modulation on the first modulated signal to obtain a second modulated signal; and sending the second modulated signal to an RFID reader, by means of which the OFDM demodulation, phase-shift keying demodulation, and decoding are performed sequentially on the second modulated signal. According to the signal processing method and device, and the RFID system of one or more embodiments of present disclosure, the RFID system can be caused to effectively utilize bandwidth, thereby achieving high-speed transmission of signals and significantly reducing a bit error ratio of signal transmission.

Abstract: A computing-in-memory circuit includes a Resistive Random Access Memory (RRAM) array and a peripheral circuit. The RRAM array comprises a plurality of memory cells arranged in an array pattern, and each memory cell is configured to store a data of L bits, L being an integer not less than 2. The peripheral circuit is configured to, in a storage mode, write more than one convolution kernels into the RRAM array, and in a computation mode, input elements that need to be convolved in a pixel matrix into the RRAM array and read a current of each column of memory cells, wherein each column of memory cells stores one convolution kernel correspondingly, and one element of the convolution kernel is stored in one memory cell correspondingly, and one element of the pixel matrix is correspondingly input into a word line that a row of memory cells connect.

Abstract: A memory device and a method for manufacturing the same, and an electronic apparatus including the memory device are provided. The memory device may include: a substrate (1001); an electrode structure on the substrate (1001), in which the electrode structure includes a plurality of first electrode layers and a plurality of second electrode layers that are alternately stacked; a plurality of vertical active regions penetrating the electrode structure; a first gate dielectric layer and a second gate dielectric layer, in which the first gate dielectric layer is between the vertical active region and each first electrode layer of the electrode structure, and the second gate dielectric layer is between the vertical active region and each second electrode layer of the electrode structure, each of the first gate dielectric layer and the second gate dielectric layer constitutes a data memory structure.

Abstract: A nanowire/nanosheet device having a ferroelectric or negative capacitance material and a method of manufacturing the same, and an electronic apparatus including the nanowire/nanosheet device are provided. According to embodiments, the semiconductor device may include: a substrate; a nanowire/nanosheet on the substrate and spaced apart from a surface of the substrate; a gate electrode surrounding the nanowire/nanosheet; a ferroelectric or negative capacitance material layer formed on a sidewall of the gate electrode; and source/drain layers at opposite ends of the nanowire/nanosheet and adjoining the nanowire/nanosheet.

Abstract: Provided is a method for optimizing a lithography quality, including: determining a wave function stray term introduced by a surface roughness of a metal film layer based on Eigen matrix method and Bloch theorem; inputting the wave function stray term into a lithography quality deviation mathematical model for calculation and simulation to obtain an influence analysis curve of a roughness of the metal film layer on a lithography quality, the influence analysis curve characterizes an influence result of the roughness of the metal film layer on the lithography quality; reducing the surface roughness of the metal film layer and/or providing a metal-dielectric multilayer film structure between a mask above a metal-dielectric unit and air according to the influence result, so as to optimize the lithography quality of the metal-dielectric unit. Provided is an apparatus for optimizing a lithography quality, an electronic device, a computer-readable storage medium and computer program product.

Abstract: A self-reference storage structure includes: three transistors, including a first transistor T1, a second transistor T2, and a third transistor T3; and two magnetic tunnel junctions, including a first magnetic tunnel junction MTJ0 and a second magnetic tunnel junction MTJ1. The first magnetic tunnel junction MTJ0 is connected in series between the first transistor T1 and the second transistor T2, and the second magnetic tunnel junction MTJ1 is connected in series between the second transistor T2 and the third transistor T3. When the first transistor T1, the second transistor T2 and the third transistor T3 are turned on, one-bit binary information is written; and when data is stored, one-bit binary write can be implemented only by applying an unidirectional current pulse.

Abstract: Provided are a semiconductor arrangement and a method for manufacturing the same. An example arrangement may comprise: a bulk semiconductor substrate; a fin formed on the substrate; a first FinFET and a second FinFET formed on the substrate, wherein the first FinFET comprises a first gate stack intersecting the fin and a first gate spacer disposed on sidewalls of the first gate stack, the second FinFET comprises a second gate stack intersecting the fin and a second gate spacer disposed on sidewalls of the second gate stack; a dummy gate spacer formed between the first FinFET and the second FinFET and intersecting the fin; a first isolation section self-aligned to a space defined by the dummy gate spacer, wherein the isolation section electrically isolates the first FinFET from the second FinFET; and a second isolation layer disposed under a bottom surface of the first isolation section.

Abstract: A photoelectric detection device, including: a vacuum sealed housing, wherein the vacuum sealed housing includes a mounting interface for mounting the photodetector array so as to form a sealed space; the photodetector array has a detection surface facing an outside of the vacuum sealed housing and configured to receive multi-channel measurement optical signals; a photoelectric conversion and synchronous acquisition circuit and a high speed transmission circuit board are placed in the vacuum sealed housing, and the photodetector array is connected to the photoelectric conversion and synchronous acquisition circuit through a signal pin of the photodetector array; the photoelectric conversion and synchronous acquisition circuit is configured to synchronously convert the multi-channel measurement optical signals obtained by the photodetector array into multi-channel digital signals; and the high speed transmission circuit board is configured to perform a serial encoding processing on the converted multi-channel