Patents Assigned to Institute of Microelectronics
  • Patent number: 11677001
    Abstract: The present disclosure discloses a semiconductor device with C-shaped channel portion, a method of manufacturing the same, and an electronic apparatus including the same. According to the embodiments, the semiconductor device may comprise a channel portion on a substrate, the channel portion including two or more curved nanosheets or nanowires spaced apart from each other in a lateral direction relative to the substrate and each having a C-shaped cross section; source/drain portions respectively located at upper and lower ends of the channel portion relative to the substrate; and a gate stack surrounding an outer circumference of each nanosheet or nanowire in the channel portion.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: June 13, 2023
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 11652103
    Abstract: The present disclosure provides a semiconductor device, a manufacturing method thereof, and an electronic device including the semiconductor device. According to an embodiment of the present disclosure, the semiconductor device may comprise: a substrate; a first device and a second device that are sequentially stacked on the substrate. Each of the first device and the second device comprises: a first source/drain layer, a channel layer, and a second source layer that are sequentially stacked from bottom to top, and a gate stack around at least a part of an outer periphery of the channel layer, wherein sidewalls of the respective channel layers of the first device and the second device extend at least partially along different crystal planes or crystal plane families.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: May 16, 2023
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Publication number: 20230140784
    Abstract: A signal processing method is applied to an RFID electronic tag, and includes: coding a digital baseband signal to obtain a coded signal; performing phase-shift keying modulation on the coded signal to obtain a first modulated signal; performing OFDM modulation on the first modulated signal to obtain a second modulated signal; and sending the second modulated signal to an RFID reader, by means of which the OFDM demodulation, phase-shift keying demodulation, and decoding are performed sequentially on the second modulated signal. According to the signal processing method and device, and the RFID system of one or more embodiments of present disclosure, the RFID system can be caused to effectively utilize bandwidth, thereby achieving high-speed transmission of signals and significantly reducing a bit error ratio of signal transmission.
    Type: Application
    Filed: September 29, 2020
    Publication date: May 4, 2023
    Applicant: INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES
    Inventors: Feng ZHANG, Zhisheng CHEN
  • Patent number: 11641787
    Abstract: The present disclosure provides a self-rectifying resistive memory, including: a lower electrode; a resistive material layer formed on the lower electrode and used as a storage medium; a barrier layer formed on the resistive material layer and using a semiconductor material or an insulating material; and an upper electrode formed on the barrier layer to achieve Schottky contact with the material of the barrier layer; wherein, the Schottky contact between the upper electrode and the material of the barrier layer is used to realize self-rectification of the self-rectifying resistive memory. Thus, no additional gate transistor or diode is required as the gate unit. In addition, because the device has self-rectifying characteristics, it is capable of suppressing read crosstalk in the cross-array.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: May 2, 2023
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Qing Luo, Hangbing Lv, Ming Liu
  • Publication number: 20230125211
    Abstract: The present application discloses a spin Hall device, a method for obtaining a Hall voltage, and a max pooling method. The spin Hall device includes a cobalt ferroboron layer. A top view and a bottom view of the spin Hall device are completely the same as a cross-shaped graph that has two axes of symmetry perpendicular to each other and equally divided by each other. The spin Hall device of the present application has non-volatility and analog polymorphic characteristics, can be used for obtaining a Hall voltage and applied to various circuits, is simple in structure and small in size, can save on-chip resources, and can meet computation requirements.
    Type: Application
    Filed: September 12, 2022
    Publication date: April 27, 2023
    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Yan CUI, Jun LUO, Meiyin YANG, Jing XU
  • Publication number: 20230124011
    Abstract: A reconfigurable PUF device based on fully electric field-controlled domain wall motion includes a voltage control layer, upper electrodes, a lower electrode, antiferromagnetic pinning layers, and a magnetic tunnel junction (MTJ). The MTJ includes, from bottom to top, a ferromagnetic reference layer, a potential barrier tunneling layer and a ferromagnetic free layer. In the device, an energy potential well is formed in a middle portion of the ferromagnetic free layer by applying a voltage to the voltage control layer to control magnetic anisotropy, and a current is fed into either of the upper electrodes to drive generation of the magnetic domain walls and pin the magnetic domain walls to the potential well. After the voltage is removed, the potential well is lowered so that the magnetic domain walls are in a metastable state, thereby either a high resistance state or a low resistance state is randomly obtained.
    Type: Application
    Filed: December 5, 2022
    Publication date: April 20, 2023
    Applicant: INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES
    Inventors: Guozhong XING, Huai LIN, Di WANG, Long LIU, Kaiping ZHANG, Guanya WANG, Yan WANG, Xiaoxin XU, Ming LIU
  • Patent number: 11631669
    Abstract: A parallel structure comprising source/drain and channel layers alternately stacked on a substrate, and gate stacks formed around peripheries of the channel layers. Each of the channel layers, the source/drain layers on upper and lower sides of the channel layer, and the gate stack formed around the channel layer, form a semiconductor device. In each semiconductor device, one of the source/drain layers is in contact with a first electrically-conductive channel disposed on an outer periphery of the active region, the other is in contact with a second electrically-conductive channel on the outer periphery of the active region, and the gate stack is in contact with a third electrically-conductive channel disposed on the outer periphery of the active region. The first electrically-conductive channel is common to the semiconductor devices, the second electrically-conductive channel is common to the semiconductor devices, and the third electronically-conductive channel is common to the semiconductor devices.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: April 18, 2023
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 11626498
    Abstract: A semiconductor memory device that may include a substrate, an array of memory cells arranged in rows and columns, bit lines and word lines. The memory cells each may include a pillar-shaped active region extending vertically, which includes source/drain regions at upper and lower ends respectively and a channel region between the source/drain regions. The channel region may include a single-crystalline semiconductor material. The memory cells each may further include a gate stack formed around a periphery of the channel region. Each of the bit lines is located below a corresponding column, and electrically connected to the lower source/drain regions of the respective memory cells in the corresponding column. Each of the word lines is electrically connected to the gate stacks of the respective memory cells in a corresponding row.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: April 11, 2023
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Publication number: 20230104404
    Abstract: A computing-in-memory circuit includes a Resistive Random Access Memory (RRAM) array and a peripheral circuit. The RRAM array comprises a plurality of memory cells arranged in an array pattern, and each memory cell is configured to store a data of L bits, L being an integer not less than 2. The peripheral circuit is configured to, in a storage mode, write more than one convolution kernels into the RRAM array, and in a computation mode, input elements that need to be convolved in a pixel matrix into the RRAM array and read a current of each column of memory cells, wherein each column of memory cells stores one convolution kernel correspondingly, and one element of the convolution kernel is stored in one memory cell correspondingly, and one element of the pixel matrix is correspondingly input into a word line that a row of memory cells connect.
    Type: Application
    Filed: July 23, 2020
    Publication date: April 6, 2023
    Applicant: INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES
    Inventors: Feng ZHANG, Renjun SONG
  • Patent number: 11616150
    Abstract: A semiconductor device with C-shaped channel portion and an electronic apparatus including the semiconductor device are disclosed. According to the embodiments, the semiconductor device may include a first semiconductor element and a second semiconductor element adjacent in a first direction. The first semiconductor element and the second semiconductor element may respectively include: a channel portion on a substrate, the channel portion including a curved nano-sheet or nano-wire with a C-shaped section; source/drain portions at upper and lower ends of the channel portion with respect to the substrate, respectively; and a gate stack surrounding a periphery of the channel portion. The channel portion of the first semiconductor element and the channel portion of the second semiconductor element may be substantially coplanar.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: March 28, 2023
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 11611353
    Abstract: A quantizer for a sigma-delta modulator, a sigma-delta modulator, and a method of shaping noise are provided. The quantizer includes: an integrator configured to generate, in a Kth sampling period, a quantization error signal for a Kth period according to an internal signal, a quantization error signal for a (K?1)th period, a filtered quantization error signal for the (K?1)th period and a filtered quantization error signal for a (K?2)th period; an integrating capacitor configured to store the quantization error signal for the Kth period, to weight the internal signal in a (K+1)th sampling period; a passive low-pass filter configured to acquire the quantization error signal for the Kth period in a Kth discharge period, and feed back the filtered quantization error signal to the integrator in a (K+1)th sampling period and a (K+2)th sampling period; and a comparator configured to quantize the quantization error signal for the Kth period.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: March 21, 2023
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Kunyu Wang, Li Zhou, Jie Chen, Minghui Chen, Ming Chen, Wenjing Xu, Chengbin Zhang
  • Patent number: 11594608
    Abstract: A gate-all-around nanowire device and a method for forming the gate-all-around nanowire device. A first fin and a dielectric layer on the first fin are formed on a substrate. The first fin includes the at least one first epitaxial layer and the at least one second epitaxial layer that are alternately stacked. The dielectric layer exposes a channel region of the first fin. A doping concentration at a lateral surface of the channel region and a doping concentration at a central region of the channel region are different from each other in the at least one second epitaxial layer. After the at least one first epitaxial layer is removed from the channel region, the at least one second epitaxial layer in the channel region serves as at least one nanowire. A gate surrounding the at least one nanowire is formed.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: February 28, 2023
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huaxiang Yin, Jiaxin Yao, Qingzhu Zhang, Zhaohao Zhang, Tianchun Ye
  • Publication number: 20230046423
    Abstract: A magnetoresistive memory cell includes a first magnetic tunnel junction, a second magnetic tunnel junction and a metal layer. The first magnetic tunnel junction and the second magnetic tunnel junction each are disposed on the metal layer; the metal layer is configured to pass write current, a projection line of an easy axis of the first magnetic tunnel junction on a plane where the metal layer is located forms a first angle against a direction of the write current, and a projection line of an easy axis of the second magnetic tunnel junction on the plane where the metal layer is located forms a second angle against a direction opposite to the direction of the write current; the first angle and the second angle are all less than 90°; the first magnetic tunnel junction and the second magnetic tunnel junction are configured to pass read current.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 16, 2023
    Applicant: INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES
    Inventors: Guozhong XING, Long LIU, Di WANG, Huai LIN, Ming LIU
  • Patent number: 11569388
    Abstract: A multi-gate FinFET including a negative capacitor connected to one of its gates, a method of manufacturing the same, and an electronic device comprising the same are disclosed. In one aspect, the FinFET includes a fin extending in a first direction on a substrate, a first gate extending in a second direction crossing the first direction on the substrate on a first side of the fin to intersect the fin, a second gate opposite to the first gate and extending in the second direction on the substrate on a second side of the fin opposite to the first side to intersect the fin, a metallization stack provided on the substrate and above the fin and the first and second gates, and a negative capacitor formed in the metallization stack and connected to the second gate.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: January 31, 2023
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Zhengyong Zhu
  • Publication number: 20230015379
    Abstract: A HfO2-based ferroelectric capacitor and a preparation method therefor, and a HfO2-based ferroelectric memory, relating to the technical field of microelectronics. The purpose of enlarging the memory window of the ferroelectric memory is achieved by inserting an Al2O3 intercalation layer having a coefficient of thermal expansion smaller than TiN between a dielectric layer and an upper electrode (TiN) of the ferroelectric capacitor. The HfO2-based ferroelectric capacitor comprises a substrate layer, a lower electrode, a dielectric layer, an Al2O3 intercalation layer, an upper electrode and a metal protection layer from bottom to top. The memory window can be increased, information misreading is effectively prevented, and therefore, the reliability of the memory is improved.
    Type: Application
    Filed: July 9, 2020
    Publication date: January 19, 2023
    Applicant: INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES
    Inventors: Qing Luo, Pengfei JIANG, Hangbing LV, Yuan Wang, Ming Liu
  • Publication number: 20230005836
    Abstract: A metallization stack and a method of manufacturing the same, and an electronic device including the metallization stack are provided. The metallization stack may include at least one interconnection line layer and at least one via hole layer arranged alternately on a substrate. At least one pair of adjacent interconnection line layer and via hole layer in the metallization stack includes: an interconnection line in the interconnection line layer, and a via hole in the via hole layer. The interconnection line layer is closer to the substrate than the via hole layer. A peripheral sidewall of a via hole on at least part of the interconnection line does not exceed a peripheral sidewall of the at least part of the interconnection line.
    Type: Application
    Filed: November 6, 2020
    Publication date: January 5, 2023
    Applicant: Institute of Microelectronics, Chinese Academy of Sciences
    Inventor: Huilong Zhu
  • Publication number: 20220416023
    Abstract: Disclosed are a semiconductor apparatus, a manufacturing method therefor, and an electronic equipment comprising the semiconductor apparatus. According to the embodiments, the semiconductor apparatus includes a first device and a second device on a substrate that are opposite each other. The first device and the second device each include a channel portion, source/drain portions on both sides of the channel portion that are connected to the channel portion, and a gate stack overlapping the channel portion. The channel portion includes a first portion extending in a vertical direction relative to the substrate and a second portion extending from the first portion in a transverse direction relative to the substrate. The second portion of the channel portion of the first device and the second portion of the channel portion of the second device extend toward or away from each other.
    Type: Application
    Filed: November 26, 2020
    Publication date: December 29, 2022
    Applicant: Institute of Microelectronics, Chinese Academy of Sciences
    Inventor: Huilong Zhu
  • Patent number: 11532756
    Abstract: A C-shaped active area semiconductor device and a method of manufacturing the same and electronic device including the semiconductor device are provided. According to embodiments, the semiconductor device includes: a channel portion extending vertically on a substrate; source/drain portions located at upper and lower ends of the channel portion relative to the substrate and along the channel portion, wherein the source/drain portion extends toward a side of the channel portion in a lateral direction relative to the substrate, so that the source/drain portions and the channel portion constitute a C-shaped structure; a gate stack that overlaps the channel portion on an inner sidewall of the C-shaped structure, wherein the gate stack has a portion surrounded by the C-shaped structure; and a back gate stack overlapping the channel portion on an outer sidewall of the C-shaped structure.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: December 20, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 11532753
    Abstract: A nanowire semiconductor device having a high-quality epitaxial layer and a method of manufacturing the same are provided. According to an embodiment, the semiconductor device may include: a substrate; one or more nanowires spaced apart from the substrate, wherein the nanowires each extend along a curved longitudinal extending direction; and one or more semiconductor layers formed around peripheries of the respective nanowires to at least partially surround the respective nanowires, wherein the respective semiconductor layers around the respective nanowires are spaced apart from each other.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: December 20, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 11532743
    Abstract: A semiconductor device with a U-shaped channel and a manufacturing method thereof and an electronic apparatus including the semiconductor device are disclosed. According to embodiments, the semiconductor device may include: a channel portion extending vertically on a substrate and having a U-shape in a plan view; source/drain portions located at upper and lower ends of the channel portion and along the U-shaped channel portion; and a gate stack overlapping the channel portion on an inner side of the U shape.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: December 20, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu