Patents Assigned to Institute of Microelectronics
  • Publication number: 20230397504
    Abstract: Provided is an all-electrically-controlled spintronic neuron device, a neuron circuit and a neural network. The neuron device includes: a bottom antiferromagnetic pinning layer; a synthetic antiferromagnetic layer formed on the bottom antiferromagnetic pinning layer; a potential barrier layer formed on the ferromagnetic free layer, wherein a region of the ferromagnetic free layer directly opposite to the potential barrier layer forms a threshold region; a ferromagnetic reference layer formed on the potential barrier layer; wherein the potential barrier layer, the ferromagnetic reference layer and the ferromagnetic free layer form a magnetic tunnel junction; a first antiferromagnetic pinning layer and a second antiferromagnetic pinning layer formed on an exposed region of the ferromagnetic free layer except the region directly opposite the potential barrier layer, and located on two sides of the potential barrier layer; and a first electrode formed on the ferromagnetic reference layer.
    Type: Application
    Filed: May 17, 2021
    Publication date: December 7, 2023
    Applicant: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Guozhong Xing, Di Wang, Ming Liu
  • Patent number: 11839085
    Abstract: Provided are a three-dimensional vertical single transistor ferroelectric memory and a manufacturing method thereof. The ferroelectric memory comprises: a substrate; an insulating dielectric layer provided at the substrate; a channel structure extending through the insulating dielectric layer and connected to the substrate, the channel structure having a source/drain region and a channel region connected to the source/drain region; and a gate stack structure arranged around the channel structure and provided in the insulating dielectric layer opposite to the channel region, the gate stack structure comprising a ferroelectric insulation layer and a gate sequentially stacked in a direction away from the channel structure. The ferroelectric memory having the above structure can replace conventional DRAMs. Therefore, the invention realizes a high intensity high speed memory.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: December 5, 2023
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huaxiang Yin, Zhaozhao Hou, Tianchun Ye, Chaolei Li
  • Patent number: 11830929
    Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof, and an electronic device including the semiconductor device. The method includes: forming a first material layer and a second material layer sequentially on a substrate; defining an active region of the semiconductor device on the substrate, the first material layer and the second material layer, wherein the active region includes a channel region; forming spacers around an outer periphery of the channel region, respectively at set positions of the substrate and the second material layer; forming a first source/drain region and a second source/drain region on the substrate and the second material layer respectively; and forming a gate stack around the outer periphery of the channel region; wherein the spacers each have a thickness varying in a direction perpendicular to a direction from the first source/drain region pointing to the second source/drain region.
    Type: Grant
    Filed: October 14, 2022
    Date of Patent: November 28, 2023
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 11827988
    Abstract: An embodiment of the present disclosure provides an etching method, having the following steps: forming a modified layer having a thickness of one or several atom layers on a selected region of a surface of a semiconductor material layer by using a modifier; and removing the modified layer. When a semiconductor is processed, this method achieves precise control over the etching thickness and improves the etching rate at the same time.
    Type: Grant
    Filed: August 18, 2022
    Date of Patent: November 28, 2023
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Xiaogen Yin, Chen Li, Anyan Du, Yongkui Zhang
  • Patent number: 11817480
    Abstract: A semiconductor device with U-shaped channel and electronic apparatus including the same are disclosed. the semiconductor device includes a first device and a second device opposite to each other on a substrate. The two devices each include: a channel portion vertically extending on the substrate and having a U-shape in a plan view; source/drain portions respectively located at upper and lower ends of the channel portion and along the U-shaped channel portion; and a gate stack overlapping the channel portion on an inner side of the U-shape. An opening of the U-shape of the first device and an opening of the U-shape of the second device are opposite to each other. At least a portion of the gate stack of the first device close to the channel portion and at least a portion of the gate stack of the second device close to the channel portion are substantially coplanar.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: November 14, 2023
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 11810902
    Abstract: A semiconductor device, a method of manufacturing the semiconductor device, and an electronic apparatus including the semiconductor device are provided. The semiconductor device may include: a plurality of element stacks, wherein each element stack includes a plurality of stacked layers of semiconductor elements, each semiconductor element includes a gate electrode and source/drain regions on opposite sides of the gate electrode; and an interconnection structure between the plurality of element stacks. The interconnection structure includes an electrical isolation layer, and a conductive structure in the electrical isolation layer. At least one of the gate electrode and the source/drain regions of each of at least a part of the semiconductor elements is in contact with and therefore electrically connected to the conductive structure of the interconnection structure at a corresponding height in a lateral direction.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: November 7, 2023
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 11810986
    Abstract: A method for integrating a surface-electrode ion trap and a silicon optoelectronic device, and an integrated structure. A silicon structure and a grating are formed on a wafer. A first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer are sequentially deposited above the wafer. An epitaxy opening is provided in the first dielectric layer to form single-photon avalanche detectors. First contacts vias connecting the detectors, and through silicon vias reaching a back surface of the wafer, are provided in the second dielectric layer and the third dielectric layer, respectively. Electrodes, the second contact vias and the third contact vias are provided in the fourth dielectric layer. The first contact vias are connected to a first electrode via the second contact vias, and the through silicon vias are connected to the first electrode and a second electrode via the third contact vias.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: November 7, 2023
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Yan Yang, Zhihua Li, Wenwu Wang
  • Patent number: 11810823
    Abstract: Semiconductor arrangements and methods of manufacturing the same. The semiconductor arrangement may include: a substrate including a base substrate, a first semiconductor layer on the substrate, and a second semiconductor layer on the first semiconductor layer; first and second fin structures formed on the substrate and extending in the same straight line, each of the first and second fin structures including at least portions of the second semiconductor layer; a first isolation part formed around the first and second fin structures on opposite sides of the straight line; first and second FinFETs formed on the substrate based on the first and second fin structures respectively; and a second isolation part between the first and second fin structures and intersecting the first and second fin structures to isolate the first and second fin structures from each other.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: November 7, 2023
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 11790968
    Abstract: The disclosure provides a spintronic device, a SOT-MRAM storage cell, a storage array and a in-memory computing circuit. The spintronic device includes a ferroelectric/ferromagnetic heterostructure, a magnetic tunnel junction, and a heavy metal layer between the ferroelectric/ferromagnetic heterostructure and the magnetic tunnel junction; the ferroelectric/ferromagnetic heterostructure includes a multiferroic material layer and a ferromagnetic layer arranged in a stacked manner, and the magnetic tunnel junction includes a free layer, an insulating layer and a reference layer arranged in a stacked manner, and the heavy metal layer is disposed between the ferromagnetic layer and the free layer. According to one or more embodiments of the disclosure, the spintronic device, the SOT-MRAM storage cell, the storage array and the in-memory computing circuit can realize deterministic magnetization inversion under the condition of no applied field assistance.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: October 17, 2023
    Assignee: INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES
    Inventors: Guozhong Xing, Huai Lin, Cheng Lu, Qi Liu, Hangbing Lv, Ling Li, Ming Liu
  • Publication number: 20230325337
    Abstract: Provided are a data transmission device and a data transmission method, which are applied to a field of an information technology. The data transmission device includes: a signal conversion module (30) and a signal transmission module (20), wherein the signal conversion module (30) is configured to convert, at a data transmitting end, an electrical signal containing a data information into a magnon signal containing the data information; the signal transmission module (20) is configured to transmit the magnon signal containing the data information to a data receiving end; and the signal conversion module (30) is further configured to convert, at the data receiving end, the magnon signal containing the data information into the electrical signal containing the data information. The data transmission method includes transmitting the data by using the magnon signal, and no voltage or current is required in a process of transmitting the data.
    Type: Application
    Filed: August 28, 2020
    Publication date: October 12, 2023
    Applicant: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Chong Bi, Ming Liu
  • Patent number: 11776607
    Abstract: The present disclosure provides a fusion memory including a plurality of memory cells, wherein each memory cell of the plurality of memory cells includes: a bulk substrate; a source and a drain on the bulk substrate; a channel extending between the source and the drain; a ferroelectric layer on the channel; and a gate on the ferroelectric layer.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: October 3, 2023
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Hangbing Lv, Qing Luo, Xiaoxin Xu, Tiancheng Gong, Ming Liu
  • Patent number: 11764310
    Abstract: A vertical storage device, a method of manufacturing the same, and an electronic apparatus including the storage device are provided. The storage device includes: a first source/drain layer located at a first height with respect to a substrate and a second source/drain layer located at a second height different from the first height; a channel layer connecting the first source/drain layer and the second source/drain layer; and a gate stack including a storage function layer, the storage function layer extending on a sidewall of the channel layer and extending in-plane from the sidewall of the channel layer onto a sidewall of the first source/drain layer and a sidewall of the second source/drain layer.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: September 19, 2023
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventor: Huilong Zhu
  • Patent number: 11756956
    Abstract: Disclosed is a semiconductor device comprising: a substrate; a vertical active region formed on the substrate and comprising a first source/drain region, a channel region, and a second source/drain region sequentially disposed in a vertical direction, the first source/drain region including a laterally extending portion extending beyond a portion of the active region above the laterally extending portion; a gate stack formed around the periphery of the channel region, the gate stack including a laterally extending portion; and a stack contact portion from above the laterally extending portion of the first source/drain region to the laterally extending portion of the first source/drain region. The stack contact portion comprises a three-layer structure sequentially disposed in the vertical direction: a lower layer portion, a middle layer portion, and an upper layer portion.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: September 12, 2023
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 11749650
    Abstract: A method of manufacturing a semiconductor device includes: providing an element stack on a carrier substrate; forming an interconnection structure connecting the element stack laterally in an area on the carrier substrate adjacent to the element stack, wherein the interconnection structure includes an electrical isolation layer and a conductive structure in the electrical isolation layer; and controlling a height of the conductive structure in the interconnection structure, so that at least a part of components to be electrically connected in the element stack are in contact and therefore electrically connected to the conductive structure at the corresponding height. Forming the conductive structure includes: forming a conductive material layer in the area; forming a mask layer covering the conductive material layer; patterning the mask layer into a pattern corresponding to the conductive structure; and using the mask layer as an etching mask to selectively etch the conductive material layer.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: September 5, 2023
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Publication number: 20230276637
    Abstract: Provided are a spin orbit torque magnetic random access memory cell, a memory array and a memory, wherein the spin orbit torque magnetic random access memory cell includes: a magnetic tunnel and a selector; the selector is a two-dimensional material based selector; the magnetic tunnel junction is arranged above or below the selector; the magnetic tunnel junction includes an antiferromagnetic layer and a free layer; the free layer is adjacent to the antiferromagnetic layer; when the selector is turned on, the memory cell is conducted, a current generates a spin current which is injected into the free layer, and a magnetization direction of the free layer is switched by the exchange bias effect between the free layer and the antiferromagnetic layer.
    Type: Application
    Filed: June 24, 2020
    Publication date: August 31, 2023
    Applicant: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Guozhong Xing, Huai Lin, Ming Liu
  • Patent number: 11728408
    Abstract: A semiconductor device and a manufacturing method thereof, and an electronic device including the semiconductor device. The semiconductor device includes: a substrate; an active region including a first source/drain region, a channel region and a second source/drain region stacked sequentially on the substrate and adjacent to each other; a gate stack formed around an outer periphery of the channel region; and spacers formed around the outer periphery of the channel region, respectively between the gate stack and the first source/drain region and between the gate stack and the second source/drain region; wherein the spacers each have a thickness varying in a direction perpendicular to a direction from the first source/drain region pointing to the second source/drain region; wherein the spacers each have the thickness gradually decreasing from a surface exposed on an outer peripheral surface of the active region to an inside of the active region.
    Type: Grant
    Filed: October 14, 2022
    Date of Patent: August 15, 2023
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Publication number: 20230253316
    Abstract: A metallization stack is provided. The metallization stack may include at least one interconnection line layer and at least one via hole layer arranged alternately on a substrate. At least one pair of adjacent interconnection line layer and via hole layer in the metallization stack includes an interconnection line in the interconnection line layer; and a via hole in the via hole layer. The via hole layer is arranged closer to the substrate than the interconnection line layer, and at least part of the interconnection line extends longitudinally in a first direction, and a sidewall of the at least part of the interconnection line in the first direction is substantially coplanar with at least upper portion of a corresponding sidewall of the via hole under the at least part of the interconnection line.
    Type: Application
    Filed: April 14, 2023
    Publication date: August 10, 2023
    Applicant: Institute Of Microelectronics, Chinese Academy Of Sciences
    Inventor: Huilong Zhu
  • Patent number: 11695074
    Abstract: There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate, and a first device and a second device formed on the substrate. Each of the first device and the second device includes a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and also a gate stack surrounding a periphery of the channel layer. The channel layer of the first device and the channel layer of the second device are substantially co-planar.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: July 4, 2023
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 11688806
    Abstract: A compact vertical semiconductor device and a manufacturing method thereof, and an electronic apparatus including the semiconductor device are provided, and the vertical semiconductor device may include: a plurality of vertical unit devices stacked on each other, in which the unit devices include respective gate stacks extending in a lateral direction, and each of the gate stacks includes a main body, an end portion, and a connection portion located between the main body and the end portion, and in a top view, a periphery of the connection portion is recessed relative to peripheries of the main body and the end portion; and a contact portion located on the end portion of each of the gate stacks, in which the contact portion is in contact with the end portion.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: June 27, 2023
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Publication number: 20230187560
    Abstract: A semiconductor device having a zigzag structure, a method of manufacturing the semiconductor device, and an electronic including the semiconductor device. The semiconductor device may include a semiconductor layer (1031) extending in zigzag in a vertical direction with respect to a substrate (1001). The semiconductor layer (1031) includes one or more first portions disposed in sequence and spaced apart from each other in the vertical direction and second portions respectively disposed on and connected to opposite ends of each first portion. A second portion at one end of each first portion extends from the one end in a direction of leaving the substrate, and a second portion at the other end of the each first portion extends from the other end in a direction of approaching the substrate. First portions adjacent in the vertical direction are connected to each other by the same second portion.
    Type: Application
    Filed: March 11, 2021
    Publication date: June 15, 2023
    Applicant: Institute of Microelectronics, Chinese Academy of Sciences
    Inventor: Huilong Zhu