Patents Assigned to Institute of Microelectronics
  • Publication number: 20220393034
    Abstract: A semiconductor device and a method of manufacturing the same, and an electronic apparatus including the semiconductor device are provided. The semiconductor device includes: an active region, on a substrate, extending substantially in a vertical direction; a gate stack formed around at least a part of a periphery of the active region, the active region including a channel region opposite to the gate stack, and a first source/drain region and a second source/drain region, and the gate stack including a gate dielectric layer, a work function tuning layer and a gate electrode material layer, and the work function tuning layer being between the gate electrode material layer and the channel region; and a first low-k dielectric layer extending from a first end of the work function tuning layer to surround a first corner of an end portion, on a side facing the channel region, of the gate electrode material layer.
    Type: Application
    Filed: June 6, 2022
    Publication date: December 8, 2022
    Applicants: Beijing Superstring Academy of Memory Technology, Institute of Microelectronics, Chinese Academy of Sciences
    Inventor: Huilong Zhu
  • Patent number: 11508809
    Abstract: The present disclosure discloses a semiconductor device and a preparation method thereof. The semiconductor device includes: an N+ substrate, a plurality of openings opening toward a back surface formed in the N+ substrate; an N? epitaxial layer formed on the N+ substrate, the N? epitaxial layer including: an active area epitaxial layer including a plurality of P++ area rings and a plurality of groove structures, wherein single groove structure is formed on single P++ area ring; a terminal area epitaxial layer including an N+ field stop ring and a plurality of P+ guard rings; a Schottky contact formed on the active area epitaxial layer, a passivation layer formed on the terminal area epitaxial layer, and ohmic contacts formed on the back surface of the N+ substrate and in the plurality of openings.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: November 22, 2022
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Yidan Tang, Xinyu Liu, Yun Bai, Shengxu Dong, Chengyue Yang
  • Patent number: 11502184
    Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof, and an electronic device including the semiconductor device. The semiconductor device includes: a substrate; an active region including a first source/drain region, a channel region and a second source/drain region stacked sequentially on the substrate and adjacent to each other; a gate stack formed around an outer periphery of the channel region; and spacers formed around the outer periphery of the channel region, respectively between the gate stack and the first source/drain region and between the gate stack and the second source/drain region; wherein the spacers each have a thickness varying in a direction parallel to a top surface of the substrate.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: November 15, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Publication number: 20220352460
    Abstract: The present disclosure provides a storage unit, a data writing method and a data reading method thereof, a memory and an electronic device. The storage unit includes a semiconductor substrate, a first insulating medium layer, a ferroelectric thin film layer, a bottom electrode, a tunnel junction, a first metal interconnection portion, a second metal interconnection portion, a third metal interconnection portion and a fourth metal interconnection portion. The first insulating medium layer is formed on the semiconductor substrate, the ferroelectric thin film layer is disposed on the first insulating medium layer, the bottom electrode is formed on the ferroelectric thin film layer, and the tunnel junction is formed on the bottom electrode. The first metal interconnection portion is connected to a first end of the bottom electrode, and the third metal interconnection portion is connected to a second end of the bottom electrode.
    Type: Application
    Filed: October 6, 2021
    Publication date: November 3, 2022
    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Meiyin YANG, Jun LUO, Yan CUI, Jing XU
  • Patent number: 11482279
    Abstract: A Static Random Access Memory (SRAM) cell that may include a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first pass-gate transistor and a second pass-gate transistor provided at two levels on a substrate. The respective transistors may be vertical transistors. The first pull-up transistor and the second pull-up transistor may be provided at a first level, and the first pull-down transistor, the second pull-down transistor, the first pass-gate transistor and the second pass-gate transistor may be provided at a second level different from the first level. A region where the first pull-up transistor and the second pull-up transistor are located and a region where the first pull-down transistor, the second pull-down transistor, the first pass-gate transistor and the second pass-gate transistor are located may at least partially overlap in a vertical direction with respect to an upper surface of the substrate.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: October 25, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 11482627
    Abstract: A C-shaped active area semiconductor device and a method of manufacturing the same and electronic device including the semiconductor device are provided. According to embodiments, the semiconductor device includes: a channel portion extending vertically on a substrate; source/drain portions located at upper and lower ends of the channel portion relative to the substrate and along the channel portion, wherein the source/drain portion extends toward a side of the channel portion in a lateral direction relative to the substrate, so that the source/drain portions and the channel portion constitute a C-shaped structure; and a gate stack that overlaps the channel portion on an inner sidewall of the C-shaped structure, wherein the gate stack has a portion surrounded by the C-shaped structure.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: October 25, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Publication number: 20220337252
    Abstract: The present disclosure relates to a logic operation circuit for computation in memory, which comprises an equivalent circuit input terminal, a reference circuit input terminal, a reset input terminal and an output terminal; wherein the equivalent circuit input terminal is configured to input the equivalent voltage of a memory computing array, the reset input terminal is configured to input a reset voltage, and the reference circuit input terminal is configured to input a reference voltage; the logic operation circuit for computation in memory outputs different output voltages according to the difference between the equivalent voltage and the reference voltage, and the output voltage is output through the output terminal; the logic operation circuit of the present disclosure has a simple structure, reduced complexity and effectively saved resources.
    Type: Application
    Filed: November 24, 2021
    Publication date: October 20, 2022
    Applicant: Nanjing Institute of Intelligent Technology, Institute of Microelectronics of the Chinese Academy of
    Inventors: Delong SHANG, Yeye ZHANG, Qingyang ZENG, Shushan QIAO, Yumei ZHOU
  • Publication number: 20220328275
    Abstract: The present disclosure discloses a power device including at least one vacuum packaged unit structure. The unit structure comprises a silicon substrate (100) and an emitter (200), a light modulator (300) and a collector (400) formed on the silicon substrate (100). On the one hand, the unified silicon-based process is compatible with the existing commercial process, so that it is easy for integration, simple for manufacture, and low in cost; on the other hand, the light modulator (300) is introduced and formed on the silicon substrate by a silicon-based process, which enhances field emission efficiency of the emitter (200), offsets the inconsistency of distances between the tips of the emitters (200) and the collector (400) caused by unevenness of the emitters, and increases the process redundancy of the cold cathode emitter.
    Type: Application
    Filed: January 20, 2021
    Publication date: October 13, 2022
    Applicant: INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES
    Inventors: Fazhan ZHAO, Jianhui BU, Jiajun LUO
  • Publication number: 20220320424
    Abstract: The disclosure discloses a selector and a preparation method thereof. The selector includes: a substrate 1; an alternating layer 2 provided on the substrate 1, the alternating layer 2 being alternately formed by a bottom electrode layer 21 and an insulating layer 22; the alternating layer 2 is provided with a U-shaped groove; a selective layer 3 and a dielectric layer 4 being sequentially deposited in a direction from an inner wall of the U-shaped groove to a center of the U-shaped groove; and a top electrode layer 5 is filled in a concave space defined by the dielectric layer 4. The selector and the preparation method according to one or more embodiments of the disclosure can address the technical problem of high leakage current of the selector in existing technology and provide a selector with low leakage current.
    Type: Application
    Filed: December 14, 2020
    Publication date: October 6, 2022
    Applicant: INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES
    Inventors: Qing LUO, Yaxin DING, Hangbing LV, Ming LIU
  • Publication number: 20220310146
    Abstract: The disclosure provides a spintronic device, a SOT-MRAM storage cell, a storage array and a in-memory computing circuit. The spintronic device includes a ferroelectric/ferromagnetic heterostructure, a magnetic tunnel junction, and a heavy metal layer between the ferroelectric/ferromagnetic heterostructure and the magnetic tunnel junction; the ferroelectric/ferromagnetic heterostructure includes a multiferroic material layer and a ferromagnetic layer arranged in a stacked manner, and the magnetic tunnel junction includes a free layer, an insulating layer and a reference layer arranged in a stacked manner, and the heavy metal layer is disposed between the ferromagnetic layer and the free layer. According to one or more embodiments of the disclosure, the spintronic device, the SOT-MRAM storage cell, the storage array and the in-memory computing circuit can realize deterministic magnetization inversion under the condition of no applied field assistance.
    Type: Application
    Filed: August 7, 2020
    Publication date: September 29, 2022
    Applicant: INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES
    Inventors: Guozhong XING, Huai LIN, Cheng LU, Qi LIU, Hangbing LV, Ling LI, Ming LIU
  • Patent number: 11447876
    Abstract: An embodiment of the present disclosure provides an etching method, having the following steps: forming a modified layer having a thickness of one or several atom layers on a selected region of a surface of a semiconductor material layer by using a modifier; and removing the modified layer. When a semiconductor is processed, this method achieves precise control over the etching thickness and improves the etching rate at the same time.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: September 20, 2022
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Xiaogen Yin, Chen Li, Anyan Du, Yongkui Zhang
  • Patent number: 11430385
    Abstract: A pixel compensation circuit including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, a second capacitor, and an organic light-emitting diode, each of the first transistor to the sixth transistor including a drain, a source and a gate.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: August 30, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Di Geng, Yue Su, Ling Li, Nianduan Lu, Ming Liu
  • Patent number: 11424323
    Abstract: A semiconductor device with a C-shaped active area and an electronic apparatus including the same is disclosed. The semiconductor device may include a first device and a second device opposite to each other on a substrate, each of which includes: a channel portion extending vertically on the substrate; source/drain portions located at the upper and lower ends of the channel portion and along the channel portion, the source/drain portions and the channel portion constitute a C-shaped structure; and a gate stack overlapping the channel portion on an inner sidewall of C-shaped structure, the gate stack has a portion surrounded by the C-shaped structure. The openings of the C-shaped structures of the two devices are opposite to each other. At least a portion of the gate stack of the first device close to the channel portion and that of the second device close to the channel portion are substantially coplanar.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: August 23, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Publication number: 20220262818
    Abstract: A storage unit, a method of manufacturing the storage unit, and a three-dimensional memory. The storage unit includes: a first conductivity-type substrate; a channel layer stacked on the first conductivity-type substrate in a first direction; a second conductivity-type conduction layer including a first part and a second part that are connected, the first part being located between the first conductivity-type substrate and the channel layer, and the second part being formed in a via hole passing through the channel layer; a channel passage layer penetrating the channel layer and the first part in a negative direction of the first direction, and extending into an interior of the first conductivity-type substrate; and an insulating layer located in the channel layer and surrounding a periphery of the channel passage layer. The first conductivity-type substrate and the second conductivity-type conduction layer provide carriers required for reading and erasing operations, respectively.
    Type: Application
    Filed: July 29, 2019
    Publication date: August 18, 2022
    Applicant: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Gang Zhang, Zongliang Huo
  • Publication number: 20220261621
    Abstract: Disclosed are an artificial sensory nervous circuit and a manufacturing method thereof. The artificial sensory nervous circuit includes a sensor (S), a first memristor (RS), and a neuron circuit, where the first memristor (RS) has a unidirectional resistance characteristic. The sensor (S) is configured to sensing an external signal and generating an excitation signal according to the external signal. The first memristor (RS) is configured to generating a response signal according to the excitation signal. The neuron circuit is configured to perform charging and discharging according to the response signal so as to output a pulse signal. With the artificial sensory nervous circuit and the manufacturing method thereof, sensitivity and habituation characteristics of biological perception are realized by using a simple circuit.
    Type: Application
    Filed: November 13, 2019
    Publication date: August 18, 2022
    Applicant: INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES
    Inventors: Qi LIU, Zuheng WU, Tuo SHI, Ming LIU, Hangbing LV, Xumeng ZHANG, Wei WANG
  • Publication number: 20220253684
    Abstract: Disclosed is an afferent neuron circuit, which includes: a resistance Rc and a volatile threshold switching device TS, wherein the volatile threshold switching device TS is provided with a parasitic capacitor Cparasitic; a first end of the resistance Rc serves as a signal input terminal, and a second end of the resistance Rc serves as a signal output terminal; and a first end of the volatile threshold switching device TS is connected to the signal output terminal, and a second end of the volatile threshold switching device TS is grounded. The afferent neuron circuit provided in the content of the present disclosure has a simple structure and good scalability and is suitable for large-scale integration.
    Type: Application
    Filed: November 29, 2019
    Publication date: August 11, 2022
    Applicant: INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES
    Inventors: Qi LIU, Xumeng ZHANG, Ming LIU, Hangbing LV, Zuheng WU
  • Publication number: 20220244872
    Abstract: The present disclosure discloses a storage method, a data processing method, a device and an apparatus based on a non-volatile memory, the method comprising: acquiring a weight value that needs to be stored in the non-volatile memory; determining a conductivity value corresponding to the weight value according to a first conversion method if the non-volatile memory is a high-resistance storage device; determining a conductivity value corresponding to the weight value according to a second conversion method which is different from the first conversion method if the non-volatile memory is a low-resistance memory device; and setting the non-volatile memory according to the conductivity value to store the weight value.
    Type: Application
    Filed: April 22, 2021
    Publication date: August 4, 2022
    Applicant: INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES
    Inventors: Feng ZHANG, Qiang HUO, Zhisheng CHEN, Qirui REN
  • Patent number: 11404568
    Abstract: A semiconductor device, including: a substrate; a first source/drain layer, a channel layer, and a second source/drain layer sequentially stacked on the substrate and adjacent to each other, and a gate stack formed around an outer circumference of the channel layer; wherein at least one interface structure is formed in at least one of the first source/drain layer and the second source/drain layer, the conduction band energy levels at both sides of the interface structure are different and/or the valence band energy levels are different.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: August 2, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Huilong Zhu, Zhenhua Wu
  • Patent number: 11380689
    Abstract: A semiconductor memory device, a method of manufacturing the same, and an electronic device including the semiconductor memory device are disclosed.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: July 5, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Publication number: 20220208258
    Abstract: A Static Random Access Memory (SRAM) cell that may include a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first pass-gate transistor and a second pass-gate transistor provided at two levels on a substrate. The respective transistors may be vertical transistors. The first pull-up transistor and the second pull-up transistor may be provided at a first level, and the first pull-down transistor, the second pull-down transistor, the first pass-gate transistor and the second pass-gate transistor may be provided at a second level different from the first level. A region where the first pull-up transistor and the second pull-up transistor are located and a region where the first pull-down transistor, the second pull-down transistor, the first pass-gate transistor and the second pass-gate transistor are located may at least partially overlap in a vertical direction with respect to an upper surface of the substrate.
    Type: Application
    Filed: October 31, 2019
    Publication date: June 30, 2022
    Applicant: INSTITUTE OF MICROELECTRONICS CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong ZHU