Abstract: The present invention relates to a semiconductor substrate, an integrated circuit having the semiconductor substrate, and methods of manufacturing the same.

Abstract: The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a source region and a drain region located in the semiconductor substrate and on respective sides of the gate, wherein at least one of the source region and the drain region comprises at least one dislocation; an epitaxial semiconductor layer containing silicon located on the source region and the drain region; and a metal silicide layer on the epitaxial semiconductor layer.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. The method comprises: forming at least one trench in a first semiconductor layer, wherein at least lower portions of respective sidewalls of the trench tilt toward outside of the trench; filling a dielectric material in the trench, thinning the first semiconductor layer so that the first semiconductor layer is recessed with respect to the dielectric material, and epitaxially growing a second semiconductor layer on the first semiconductor layer, wherein the first semiconductor layer and the semiconductor layer comprise different materials from each other. According to embodiments of the disclosure, defects occurring during the heteroepitaxial growth can be effectively suppressed.

Abstract: The invention discloses an etch-back method for planarization at the position-near-interface of an interlayer dielectric (ILD), comprising: depositing or growing a thick layer of SiO2 by the chemical vapor deposition or oxidation method on a surface of a wafer; spin-coating a layer of SOG and then performing a heat treatment to obtain a relatively uniform stack structure; perform an etch-back on the SOG using a plasma etching, and stopping when approaching the position-near-interface of SiO2; performing a plasma etch-back on the remaining SOG/SiO2 structure at the position-near-interface until achieving a desired thickness. Since a two-step etching at the position-near-interface is employed, an extremely good smooth surface of the ILD is obtained. That is, a planar and tidy surface of the ILD is obtained not only in the center region, but also even at the edge of the wafer.

Abstract: A flash memory device includes a semiconductor substrate, a gate stack formed on the semiconductor substrate; a channel region below the gate stack; spacers outside the gate stack; and source/drain regions outside the channel region and in the semiconductor substrate, in which the gate stack includes a first gate dielectric layer on the channel region; a first conductive layer covering an upper surface of the first gate dielectric layer and inner walls of the spacers; a second gate dielectric layer covering a surface of the first conductive layer; and a second conductive layer covering a surface of the second gate dielectric layer. A method for manufacturing a flash memory device disclosed herein.

Abstract: The present invention provides a semiconductor structure comprising a substrate, a gate stack, a sidewall, a base region, source/drain regions, and a support structure, wherein: the base region is located above the substrate, and is separated from the substrate by the void; said support structure is located on both sides of the void, in which part of the support isolation structure is connected with the substrate; the gate stack is located above the base region, said sidewall surrounding the gate stack; said source/drain regions are located on both sides of the gate stack, the base region and the support isolation structure, in which the stress in the source/drain regions first gradually increases and then gradually decreases along the height direction from the bottom. The present invention also provides a manufacturing method for the semiconductor structure. The present invention is beneficial to suppress the short channel effect, as well as to provide an optimum stress to the channel.

Abstract: The present invention discloses a semiconductor device, which comprises: a substrate, and a shallow trench isolation in the substrate, characterized in that, the semiconductor device further comprises a stress release layer between the substrate and the shallow trench isolation. In the semiconductor device and the method for manufacturing the same according to the present invention, the stresses accumulated during the formation of the STI can be released by interposing the stress release layer made of a softer material between the substrate and the STI, thereby reducing the leakage current of the substrate of the device and improving the device reliability.

Abstract: The present disclosure provides a method for forming and controlling a molecular level SiO2 interface layer, mainly comprising: cleansing before growing the SiO2 interface layer, growing the molecular level ultra-thin SiO2 interface layer; and controlling reaction between high-K gate dielectric and the SiO2 interface layer to further reduce the SiO2 interface layer. The present disclosure can strictly prevent invasion of oxygen during process integration. The present disclosure can obtain a good-quality high-K dielectric film having a small EOT. The manufacturing process is simple and easy to integrate. It is also compatible with planar CMOS process, and can satisfy requirement of high-performance nanometer level CMOS metal gate/high-K device of 45 nm node and below.

Abstract: A method for manufacturing a semiconductor structure comprises: providing a substrate (100) on which a dummy gate stack is formed, forming a spacer (240) at sidewalls of the dummy gate stack, and forming a source/drain region (110) and a source/drain extension region (111) at both sides of the dummy gate stack; removing at least part of the spacer (240), to expose at least part of the source/drain extension region (111); forming a contact layer (112) on the source/drain region (110) and the exposed source/drain extension region (111), the contact layer (112) being [made of] one of CoSi2, NiSi and Ni(Pt)Si2-y or combinations thereof, and a thickness of the contact layer (112) being less than 10 nm. Correspondingly, the present invention further provides a semiconductor structure which is beneficial to reducing contact resistance and can maintain excellent performance in a subsequent high temperature process.

Abstract: A Field Effect Transistor (FET) and a method of manufacturing the same are provided. The FET may include a substrate; a source and a drain, one of which is formed on a bulge formed on a top surface of the substrate, and the other of which is formed in the substrate below but laterally offset from the bulge; a gate formed at a position where the bulge and the top surface of the substrate join each other; and a gate dielectric layer formed between the gate and the bulge and also between the gate and the top surface of the substrate. The FET has a vertical configuration, where the source is disposed on top of the bulge while the drain is disposed in the substrate, that is, the source and the drain are not in one same plane. As a result, the FET may have its area significantly reduced. Therefore, it is possible to improve an integration density of an IC and thus reduce cost.

Abstract: A well region formation method and a semiconductor base in the field of semiconductor technology are provided. A method comprises: forming isolation regions in a semiconductor substrate to isolate active regions; selecting at least one of the active regions, and forming a first well region in the selected active region; forming a mask to cover the selected active region, and etching the rest of the active regions, so as to form grooves; and growing a semiconductor material by epitaxy to fill the grooves. Another method comprises: forming isolation regions in a semiconductor substrate for isolating active regions; forming well regions in the active regions; etching the active regions to form grooves, such that the grooves have a depth less than or equal to a depth of the well regions; and growing a semiconductor material by epitaxy to fill the grooves.

Abstract: A semiconductor device, which comprises: a semiconductor substrate; a channel region on the semiconductor substrate, said channel region including a quantum well structure; a source region and a drain region on the sides of the channel region; a gate structure on the channel region; wherein the materials for the channel region, the source region and the drain region have different energy bands, and a tunneling barrier structure exists between the source region and the channel region.

Abstract: A semiconductor device comprises a semiconductor substrate on an insulating layer; and a second gate that is located on the insulating layer and is embedded at least partially in the semiconductor substrate. A method for forming a semiconductor device comprises: forming a semiconductor substrate on an insulating layer; forming a void within the semiconductor substrate, with the insulating layer being exposed by the void; and forming a second gate, with the void being filled with at least one part of the second gate. It facilitates the reduction of the short channel effects, resistances of the source and drain regions, and parasitic capacitances.

Abstract: The present invention provides a semiconductor structure, comprising: a substrate; a gate stack located on the substrate and comprising at least a gate dielectric layer and a gate electrode layer; source/drain regions, located in the substrate on both sides of the gate stack; an STI structure, located in the substrate on both sides of the source/drain regions, wherein the cross-section of the STI structure is trapezoidal, Sigma-shaped or inverted trapezoidal depending on the type of the semiconductor structure. Correspondingly, the present invention further to provides a method of manufacturing the semiconductor structure.

Abstract: A FinFET and a method for manufacturing the same are disclosed. In one aspect, the method comprises forming a semiconductor fin having trapezoid cross-section. The method also includes forming one of a source region and a drain region. The method also includes forming a sacrificial spacer. The method also includes forming another one of the source region and the drain region using the sacrificial spacer as a mask. The method also includes removing the sacrificial spacer. The method also includes forming a gate stack in place of the sacrificial spacer, the gate stack comprising a gate conductor and a gate dielectric isolating the gate conductor from the semiconductor fin.

Abstract: Semiconductor structures and methods for manufacturing the same are disclosed. The semiconductor structure comprises: a gate stack formed on a semiconductor substrate; a super-steep retrograde island embedded in said semiconductor substrate and self-aligned with said gate stack; and a counter doped region embedded in said super-steep retrograde island, wherein said counter doped region has a doping type opposite to a doping type of said super-steep retrograde island. The semiconductor structures and the methods for manufacturing the same facilitate alleviating short channel effects.

Abstract: A method of manufacturing a semiconductor structure, which comprises the steps of: providing a substrate, forming a fin on the substrate, which comprises a central portion for forming a channel and an end portion for forming a source/drain region and a source/drain extension region; forming a gate stack to cover the central portion of the fin; performing light doping to form a source/drain extension region in the end portion of the fin; forming a spacer on sidewalls of the gate stack; performing heavy doping to form a source/drain region in the end portion of the fin; removing at least a part of the spacer to expose at least a part of the source/drain extension region; forming a contact layer on an upper surface of the source/drain region and an exposed area of the source/drain extension region. Correspondingly, the present invention also provides a semiconductor structure.

Abstract: A method for manufacturing a small-size fin-shaped structure, comprising: forming a first mask layer and a second mask layer on a substrate in sequence; etching the first mask layer and the second mask layer to form a hard mask pattern, wherein a second mask layer pattern is wider than a first mask layer pattern; eliminating the second mask layer pattern; and performing a dry etching of the substrate by taking the first mask layer pattern as a mask, so as to form a fin-shaped structure. According to the method for manufacturing a small-size fin-shaped structure of the present invention, firstly a large-size hard mask is prepared, then a width controllable small-size hard mask is prepared through a wet corrosion, and finally the bulk silicon wafer is etched, so as to obtain the required small-size fin-shaped structure, thereby improving the electrical properties and the integration level of the device, simplifying the processes and reducing the cost.

Abstract: The invention provides a semiconductor device comprising: a substrate; a gate, which is formed on the substrate; a source and a drain, which are located on opposite sides of the gate, respectively; a contact, which contacts with the source and/or the drain, wherein the contact has an enlarged end at an end which is in contact with the source and/or the drain. In the present invention, since the contact area of the contact is increased on the interface in contact with the source/the drain, the contact resistance can be reduced, and thus the performances of the semiconductor device can be guaranteed/improved. The present invention further provides a method of fabricating the semiconductor device (especially the contact therein) as previously described.

Abstract: A semiconductor device and a method for manufacturing the same, the method comprising: providing a semiconductor substrate; forming a dummy gate area on the substrate, forming spacers on sidewalls of the gate area, and forming source and drain areas in the semiconductor substrate on both sides of the dummy gate area, the dummy gate area comprising an interface layer and a dummy gate electrode; forming a dielectric cap layer on the dummy gate area and source and drain areas; planarizing the device with the dielectric cap layer on the source and drain areas as a stop layer; further removing the dummy gate electrode to expose the interface layer; and forming replacement gate area on the interface layer. The thickness of the gate groove may be controlled by the thickness of the dielectric cap layer, and the replacement gates of desired thickness and width may be further formed upon requirements. Thus, the aspect ratio of the gate groove is reduced and a sufficient low gate resistance is ensured.