Abstract: A transistor device comprising epitaxial LDD and Halo regions and a method of manufacturing the same are disclosed.

Abstract: A method for forming titanium nitride by PVD is disclosed, comprising: generating ions of a noble gas by glow discharge under a vacuum condition that a nitrogen gas and the noble gas are supplied; nitriding a surface of a wafer and a surface of a titanium target with the nitrogen gas; bombarding the surface of the titanium target with the ions of the noble gas after they are accelerated in an electric field so that titanium ions and titanium nitride are sputtered; and forming a titanium nitride layer by depositing titanium nitride on the surface of the wafer in a magnetic field, while titanium ions are injected into the surface of the wafer so that stress is introduced into the titanium nitride layer, wherein non-crystallization fraction of the titanium nitride layer and stress in the titanium nitride layer are increased by increasing kinetic energy of titanium ions which are injected into the surface of the wafer.

Abstract: The present invention provides a semiconductor structure comprising a substrate, a gate stack, a sidewall, a base region, source/drain regions, and a support structure, wherein: the base region is located above the substrate, and is separated from the substrate by the void; said support structure is located on both sides of the void, in which part of the support isolation structure is connected with the substrate; the gate stack is located above the base region, said sidewall surrounding the gate stack; said source/drain regions are located on both sides of the gate stack, the base region and the support isolation structure, in which the stress in the source/drain regions first gradually increases and then gradually decreases along the height direction from the bottom. The present invention also provides a manufacturing method for the semiconductor structure. The present invention is beneficial to suppress the short channel effect, as well as to provide an optimum stress to the channel.

Abstract: A transistor device comprising epitaxial LDD and Halo regions and a method of manufacturing the same are disclosed.

Abstract: A 3D integrated circuit structure comprises a first chip, wherein the first chip comprises: a substrate; a semiconductor device formed on the substrate and a dielectric layer formed on both the substrate and the semiconductor device; a conductive material layer formed within a through hole penetrating through both the substrate and the dielectric layer; a stress releasing layer surrounding the through hole; and a first interconnecting structure connecting the conductive material layer with the semiconductor device. By forming a stress releasing layer to partially release the stress caused by the conductive material in the via, the stress caused by mismatch of CTE between the conductive material and the semiconductor (for example, silicon) surrounding it can be reduced, thereby enhancing the performance of the semiconductor device and the corresponding 3D integrated circuit consisting of the semiconductor devices.

Abstract: The present invention discloses a semiconductor device, which comprises a substrate, a buffer layer on the substrate, an inversely doped isolation layer on the buffer layer, a barrier layer on the inversely doped isolation layer, a channel layer on the barrier layer, a gate stack structure on the channel layer, and source and drain regions at both sides of the gate stack structure, characterized in that the buffer layer and/or the barrier layer and/or the inversely doped isolation layer are formed of SiGe alloys or SiGeSn alloys, and the channel layer is formed of a GeSn alloy. The semiconductor device according to the present invention uses a quantum well structure of SiGe/GeSn/SiGe to restrict transportation of carriers, and it introduces a stress through lattice mis-match to greatly increase the carrier mobility, thus improving the device driving capability so as to be adapted to high-speed and high-frequency application.

Abstract: The present invention discloses a semiconductor device, comprising: a substrate, a channel layer epitaxially grown in the substrate, a gate stack structure on the channel layer, gate spacers on both sides of the gate stack structure, and source/drain areas on both sides of the channel layer in the substrate, characterized in that the carrier mobility of the channel layer is higher than that of the substrate. In accordance with the semiconductor device and the method of manufacturing the same in the present invention, forming the device channel region by filling the trench with epitaxial high-mobility materials in a gate last process can enhance the carrier mobility in the channel region, thereby the device response speed is substantially improved and the device performance is greatly enhanced.

Abstract: The present application provides a p-type semiconductor device and a method for manufacturing the same. The structure of the device comprises: a semiconductor substrate; a channel region positioned in the semiconductor substrate; a gate stack which is positioned on the channel region comprising a gate dielectric layer and a gate electrode, wherein the gate dielectric layer is positioned on the channel region and the gate electrode is positioned on the gate dielectric layer; and source/drain regions positioned at the two sides of the channel region and embedded into the semiconductor substrate; wherein the element Al is distributed in at least one of the upper surface, the bottom surface of the gate dielectric layer and the bottom surface of the gate electrode. The embodiments of the present invention are applicable for manufacturing MOSFET.

Abstract: The present disclosure provides a method for manufacturing a semiconductor field effect transistor, comprising: forming a semiconductor substrate having a local Silicon-on-Insulator (SOI) structure, which comprises a local buried isolation dielectric layer; forming a fin on a silicon substrate above the local buried isolation dielectric layer; forming a gate stack structure on a top and on side faces of the fin; forming source/drain structures in the fin at both sides of the gate stack structure; and metallizing. The present disclosure uses a conventional top-to-bottom process based on quasi-plane, which has a good compatibility with CMOS planar processes. Also, the method can suppress short channel effects and help to reduce the dimensions of MOSFETs.

Abstract: The invention relates to a transistor and a method for manufacturing the transistor. The transistor according to an embodiment of the invention may comprise: a substrate which comprises at least a back gate of the transistor, an insulating layer and a semiconductor layer stacked sequentially, wherein the back gate of the transistor is used for adjusting the threshold voltage of the transistor; a gate stack formed on the semiconductor layer, wherein the gate stack comprises a gate dielectric and a gate electrode formed on the gate dielectric; a spacer formed on sidewalls of the gate stack; and a source region and a drain region located on both sides of the gate stack, respectively, wherein the height of the gate stack is lower than the height of the spacer. The transistor enables the height of the gate stack to be reduced and therefore the performance of the transistor is improved.

Abstract: Provided is a semiconductor structure and a method for manufacturing the same. By the channel reestablishment, the tops of the source/drain regions located on both sides of the spacers are higher than bottoms of the gate stack structure and the spacers, and the source/drain regions laterally extend below the bottoms of the gate stack structure and the spacers and exceed the spacers, thereby reaching the right below of the gate stack structure. Thus, the elevated source/drain MOSFET is obtained. The semiconductor structure reduces the number of process steps, improves efficiency and decreases the cost.

Abstract: The present invention provides a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device comprises: providing a silicon substrate having a gate stack structure formed thereon and having {100} crystal indices; forming an interlayer dielectric layer coving a top surface of the silicon substrate; forming a first trench in the interlayer dielectric layer and/or in the gate stack structure, the first trench having an extension direction being along <110> crystal direction and perpendicular to that of the gate stack structure; and filling the first trench with a first dielectric layer, wherein the first dielectric layer is a tensile stress dielectric layer. The present invention introduces a tensile stress in the transverse direction of a channel region by using a simple process, which improves the response speed and performance of semiconductor devices.

Abstract: The present invention provides a semiconductor structure, which comprises: a substrate, a semiconductor base, a semiconductor auxiliary base layer, a cavity, a gate stack, a sidewall spacer, and a source/drain region, wherein the gate stack is located on the semiconductor base; the sidewall spacer is located on the sidewalls of the gate stack; the source/drain region is embedded in the semiconductor base and is located on both sides of the gate stack; the cavity is embedded in the substrate; the semiconductor base is suspended above the cavity, the thickness of the middle portion of the semiconductor base is greater than the thickness of the two end portions of the semiconductor base in the direction of the length of the gate, and the two end portions of the semiconductor base are connected to the substrate in the direction of the width of the gate; and the semiconductor auxiliary base layer is located on the sidewall of the semiconductor base and has an opposite doping type to that of the source/drain region

Abstract: There is provided a semiconductor structure and a method for manufacturing the same. The semiconductor structure according to the present invention comprises: a semiconductor substrate; a channel region formed on the semiconductor substrate; a gate stack formed on the channel region; and source/drain regions formed on both sides of the channel region and embedded in the semiconductor substrate. The gate stack comprises: a gate dielectric layer formed on the channel region; and a conductive layer positioned on the gate dielectric layer. For an nMOSFET, the conductive layer has a compressive stress to apply a tensile stress to the channel region; and for a pMOSFET, the conductive layer has a tensile stress to apply a compressive stress to the channel region.

Abstract: An analog front circuit for a medical device includes an automatic gain control loop and a 2-order-3-bit-quantization Sigma-Delta analog-to-digital converter. The automatic gain control loop is configured to implement automatic control of loop gain and output an analog signal to the 2-order-3-bit-quantization Sigma-Delta analog-to-digital converter. The 2-order-3-bit-quantization Sigma-Delta analog-to-digital converter is configured to convert the analog signal output from the automatic gain control loop into a digital code and output the digital code to a DSP for processing.

Abstract: A method of manufacturing a sub-wavelength extreme ultraviolet metal transmission grating is disclosed. In one aspect, the method comprises forming a silicon nitride self-supporting film window on a back surface of a silicon-based substrate having both surfaces polished, then spin-coating a silicon nitride film on a front surface of the substrate with an electron beam resist HSQ. Then, performing electron beam direct writing exposure on the HSQ, developing and fixing to form a plurality of grating line patterns and a ring pattern surrounding the grating line patterns. Then depositing a chrome material on the front surface of the substrate through magnetron sputtering. Then, removing the chrome material inside the ring pattern. Then, growing a gold material on the front surface of the substrate through atomic layer deposition.

Abstract: The present invention provides a method for manufacturing contact holes in a CMOS device by using a gate-last process, comprising: forming high-K dielectrics/metal gates (HKMG) of a first type MOS; forming and metalizing lower contact holes of the source/drain of a first type MOS and a second type MOS as well as forming HKMG of a second type MOS simultaneously, wherein the lower contact holes of the source/drain are filled with the same material as that used by the metal gate of the second type MOS; forming and metalizing contact holes of metal gates of a first type MOS and a second type MOS as well as upper contact holes of the source/drain, wherein the upper contact holes of the source/drain are aligned with the lower contact holes of the source/drain. The method reduces the difficulty of contact hole etching and metal deposition, simplifies the process steps, and increases the reliability of the device.

Abstract: The present invention provides a semiconductor device structure and a method for manufacturing the same. The method comprises: providing a semiconductor substrate, forming a first insulating layer on the surface of the semiconductor substrate; forming a shallow trench isolation embedded in the first insulating layer and the semiconductor substrate; forming a stripe-type trench embedded in the first insulating layer and the semiconductor substrate; forming a channel region in the trench; forming a gate stack line on the channel region and source/drain regions on opposite sides of the channel region. Embodiments of the present invention are applicable to manufacture of semiconductor devices.

Abstract: A semiconductor device and its manufacturing method are provided. The semiconductor device comprises: a semiconductor substrate of a first semiconductor material, a gate structure on the semiconductor substrate, a crystal lattice dislocation line in a channel under the gate structure for generating channel stress, wherein the crystal lattice dislocation line being at an angle to the channel.

Abstract: The present invention provides a semiconductor device. The semiconductor device comprises contact plugs that comprise a first contact plug formed by a first barrier layer arranged on the source and drain regions and a tungsten layer arranged on the first barrier layer; and second contact plugs comprising a second barrier layer arranged on both of the metal gate and the first contact plug and a conductive layer arranged on the second barrier layer. The conductivity of the conductive layer is higher than that of the tungsten layer. A method for forming the semiconductor device is also provided. The present invention provides the advantage of enhancing the reliability of the device when using the copper contact technique.