Abstract: Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the method comprises: sequentially forming a sacrificial layer and a semiconductor layer on a substrate; forming a first cover layer on the semiconductor layer; forming an opening extending into the substrate with the first cover layer as a mask; selectively removing at least a portion of the sacrificial layer through the opening, and filling an insulating material in a gap due to removal of the sacrificial layer; forming one of source and drain regions in the opening; forming a second cover layer on the substrate; forming the other of the source and drain regions with the second cover layer as a mask; removing a portion of the second cover layer; and forming a gate dielectric layer, and forming a gate conductor in the form of spacer on a sidewall of a remaining portion of the second cover layer.

Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising: forming an insulating isolation layer on a substrate; forming an insulating isolation layer trench in the insulating isolation layer; forming an active region layer in the insulating isolation layer trench; forming a semiconductor device structure in and above the active region layer; characterized in that the carrier mobility of the active region layer is higher than that of the substrate. Said active region is formed of a material different from that of the substrate, the carrier mobility in the channel region is enhanced, thereby the device response speed is improved and the device performance is enhanced. Unlike the existing STI manufacturing process, for the present invention, an STI is formed first, and then filling is performed to form an active region, thus avoiding the problem of generation of holes in STI, and improving the device reliability.

Abstract: The invention provides a graphene device structure and a method for manufacturing the same, the device structure comprising a graphene layer; a gate region in contact with the graphene layer; semiconductor doped regions formed in the two opposite sides of the gate region and in contact with the graphene layer, wherein the semiconductor doped regions are isolated from the gate region; a contact formed on the gate region and contacts formed on the semiconductor doped regions. The on-off ratio of the graphene device is increased through the semiconductor doped regions without increasing the band gap of the graphene material, i.e., without affecting the mobility of the material or the speed of the device, thereby increasing the applicability of the graphene material in CMOS devices.

Abstract: A method for fabricating black silicon by using plasma immersion ion implantation is provided, which includes: putting a silicon wafer into a chamber of a black silicon fabrication apparatus; adjusting processing parameters of the black silicon fabrication apparatus to preset scales; generating plasmas in the chamber of the black silicon fabrication apparatus; implanting reactive ions among the plasmas into the silicon wafer, and forming the black silicon by means of the reaction of the reactive ions and the silicon wafer. The method can form the black silicon which has a strong light absorption property and is sensitive to light, and has advantages of high productivity, low cost and simple production process.

Abstract: The present application discloses provides a method for planarizing an interlayer dielectric layer, comprising the steps of: providing a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack, performing a first RIE on the multilayer structure, in which a reaction chamber pressure is controlled in such a manner that an etching rate of the portion of the at least one sacrificial layer at a center of a wafer is higher than that at an edge of the wafer, so as to obtain a concave etching profile; performing a second RIE on the multilayer structure to completely remove the sacrificial layer and a part of the insulating layer, so as to obtain the insulating layer having a planar surface which serves as an interlayer dielectric layer.

Abstract: The present disclosure relates to the field of microelectronics manufacture and memories. A three-dimensional multi-bit non-volatile memory and a method for manufacturing the same are disclosed. The memory comprises a plurality of memory cells constituting a memory array. The memory array may comprise: a gate stack structure; periodically and alternately arranged gate stack regions and channel region spaces; gate dielectric layers for discrete charge storage; periodically arranged channel regions; source doping regions and drain doping regions symmetrically arranged to each other; bit lines led from the source doping regions and the drain doping regions; and word lines led from the gate stack regions. The gate dielectric layers for discrete charge storage can provide physical storage spots to achieve single-bit or multi-bit operations, so as to achieve a high storage density.

Abstract: An S/D region including a first region and a second region is provided. The first region is located, with at least a partial thickness, in the substrate. The second region is formed on the first region and made of a material different from that of the first region. A method for forming an S/D region is further provided, and the method includes: forming trenches at both sides of a gate stack structure in a substrate; forming a first semiconductor layer, wherein at least a part of the first semiconductor layer is filled into the trenches; and forming a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer is made of a material different from that of the first semiconductor layer. A contact hole and a forming method thereof are also provided which may increase the contact area between a contact hole and a contact region, and reduce the contact resistance.

Abstract: A method of manufacturing a semiconductor device is provided, in which after forming a gate stack and a first spacer thereof, a second spacer and a third spacer are formed; and then an opening is formed between the first spacer and the third spacer by removing the second spacer. The range of the formation for the raised active area 220 is limited by forming an opening 214 between the first spacer 208 and the third spacer 212. The raised active area 220 is formed in the opening 214 in a self-aligned manner, so that a better profile of the raised active area 220 may be achieved and the possible shorts between adjacent devices caused by an unlimited manner may be avoided. Moreover, based on such a manufacturing method, it is easy to make the gate electrode 204 to be flushed with the raised active area 220, and is also easy to implement the dual stress nitride process so as to increase the mobility of the device.

Abstract: A trench isolation structure and a method of forming the same are provided. The trench isolation structure includes: a semiconductor substrate, and trenches formed in the semiconductor substrate and filled with a dielectric layer, where the material of the dielectric layer is a crystalline material. By using the present invention, the size of the divot can be reduced, and device performances can be improved.

Abstract: A manufacturing method of a MOS device with memory function is provided, which includes: providing a semiconductor substrate, a surface of the semiconductor substrate being covered by a first dielectric layer, a metal interconnect structure being formed in the first dielectric layer; forming a second dielectric layer overlying a surface of the first dielectric layer and the metal interconnect structure; forming an opening in the second dielectric layer, a bottom of the opening revealing the metal interconnect structure; forming an alloy layer at the bottom of the opening, material of the alloy layer containing copper and other metal; and performing a thermal treatment to the alloy layer and the metal interconnect structure to form, on the surface of the metal interconnect structure, a compound layer containing oxygen element. The compound layer containing oxygen element and the MOS device formed in the semiconductor substrate constitute a MOS device with memory function.

Abstract: A FinFET and a method for manufacturing the same are disclosed. The FinFET comprises an etching stop layer on a semiconductor substrate; a semiconductor fin on the etching stop layer; a gate conductor extending in a direction perpendicular to a length direction of the semiconductor fin and covering at least two side surfaces of the semiconductor fin; a gate dielectric layer between the gate conductor and the semiconductor fin; a source region and a drain region which are provided at two ends of the semiconductor fin respectively; and an interlayer insulating layer adjoining the etching stop layer below the gate dielectric layer, and separating the gate conductor from the etching stop layer and the semiconductor fin. A height of the fin of the FinFET is approximately equal to a thickness of a semiconductor layer for forming the semiconductor fin.

Abstract: The present application discloses a semiconductor structure and method for manufacturing the same. The semiconductor structure comprises: an SOI substrate and a MOSFET formed on the SOI substrate, wherein the SOI substrate comprises, in a top-down fashion, an SOI layer, a first buried insulator layer, a buried semiconductor layer, a second buried insulator layer, and a semiconductor substrate, the buried semiconductor layer including a backgate region including a portion of the buried semiconductor layer doped with a dopant of a first polarity; the MOSFET comprises a gate stack and source/drain regions, the gate stack being formed on the SOI layer, and the source/drain regions being formed in the SOI layer at opposite sides of the gate stack; and the backgate region includes a counter-doped region, the counter-doped region is self-aligned with the gate stack and includes a dopant of a second polarity, and the second polarity is opposite to the first polarity.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. In one embodiment, the semiconductor device may comprise a semiconductor layer, a fin formed by patterning the semiconductor layer, and a gate stack crossing over the fin. The fin may comprise a doped block region at the bottom portion thereof. According to the embodiment, it is possible to effectively suppress current leakage at the bottom portion of the fin by the block region.

Abstract: A hybrid channel semiconductor device and a method for forming the same are provided.

Abstract: A method for manufacturing a semiconductor device is provided. The method comprises providing a semiconductor substrate; forming a dummy gate structure and a spacer surrounding the dummy gate structure on the semiconductor substrate; forming source/drain regions on both sides of the gate structure within the semiconductor substrate using the dummy gate structure and the spacer as a mask; forming an interlayer dielectric layer on the upper surface of the semiconductor substrate, the upper surface of the interlayer dielectric layer being flush with the upper surface of the dummy gate structure; removing at least a part of the dummy gate structure so as to form a trench surrounded by the spacer; performing tilt angle ion implantation into the semiconductor substrate using the interlayer dielectric layer and spacer as a mask so as to form an asymmetric Halo implantation region; sequentially forming a gate dielectric layer and a metal gate in the trench.

Abstract: A method for removing a metallic nanotube, which is formed on a substrate in a first direction, includes forming a plurality of conductors in a second direction crossing the first direction, electrically contacting the plurality of conductors with metallic nanotube, respectively, forming at least two voltage-applying electrodes on the conductors, each of which electrically contacting at least one of the conductors, and applying voltages to at least some of the conductors through the voltage-applying electrodes, respectively. Among the conductors to which the voltages are respectively applied, every two adjacent conductors have an electrical potential difference created therebetween, so as to burn out the metallic nanotube.

Abstract: A semiconductor device manufacturing method, comprising: providing a semiconductor substrate, on which a gate conductor layer as well as a source region and a drain region positioned on both sides of the gate conductor layer are provided, forming an etch stop layer on the semiconductor substrate, forming an LTO layer on the etch stop layer, chemical mechanical polishing the LTO layer, forming an SOG layer on the polished LTO layer, the etch stop layer, LTO layer and SOG layer forming a front metal insulating layer, back etching the SOG layer and etch stop layer of the front metal insulating layer to expose the gate conductor layer, and removing the gate conductor layer.

Abstract: The invention relates to a method for forming a semiconductor structure, comprising: providing a semiconductor substrate which comprises a dummy gate formed thereon, a spacer surrounding the dummy gate, source and drain regions formed on two sides of the dummy gate, respectively, and a channel region formed in the semiconductor substrate and below the dummy gate; removing the dummy gate to form a gate opening; forming a stressed material layer in the gate opening; performing an annealing to the semiconductor substrate, the stressed material layer having tensile stress characteristics during the annealing; removing the stressed material layer in the gate opening; and forming a gate in the gate opening. By the above steps, the stress memorization technique can be applied to the pMOSFET.

Abstract: The present disclosure provides a resistive random memory cell and a resistive random memory. The resistive random memory cell comprises an upper electrode, a resistive layer, an intermediate electrode, an asymmetric tunneling barrier layer, and a lower electrode. The upper electrode, the resistive layer, and the intermediate electrode constitute a resistive storage portion. The intermediate electrode, the asymmetric tunneling barrier layer, and the lower electrode constitute a selection portion. The resistive storage portion and the selection portion share the intermediate electrode. The selection portion may be disposed above or under the resistive storage portion. The asymmetric tunneling barrier layer comprises at least two materials having different barrier heights, and is configured for rectifying forward tunneling current and reverse tunneling current flowing through the resistive random memory cell.

Abstract: A method of manufacturing a semiconductor device is disclosed. In one embodiment, the method comprises: forming a gate stack on a substrate; etching the substrate on both sides of the gate stack to form C-shaped source/drain grooves; and wet-etching the C-shaped source/drain grooves to form ?-shaped source/drain grooves. With this method, it is possible to effectively increase stress applied to a channel region, to accurately control a depth of the source/drain grooves, and to reduce roughness of side walls and bottom portions of the grooves and thus reduce defects by etching the C-shaped source/drain grooves and then further wet-etching them to form the ?-shaped source/drain grooves.