Abstract: The present application discloses a method for etching a Mo-based metal gate stack with an aluminum nitride barrier, comprising the steps of forming a SiO2 interface layer, a high K dielectric layer, a Mo-based metal gate layer, an AlN barrier layer, a silicon gate layer and a hard mask in sequence on a semiconductor substrate; performing lithography on the semiconductor substrate with the SiO2 interface layer, the high K dielectric layer, the Mo-based metal gate layer, the AlN barrier layer, the silicon gate layer and the hard mask using a photoresist, and etching the hard mask; removing the photoresist, and performing an anisotropic etching for silicon gate with high selectivity to the underlying AlN barrier layer and metal gate by dry etching using the hard mask; performing an anisotropic etching for the AlN barrier layer, the Mo-based metal gate layer, and the high K dielectric layer by a dry etching.

Abstract: The present invention provides a method for integrating the dual metal gates and the dual gate dielectrics into a CMOS device, comprising: growing an ultra-thin interfacial oxide layer or oxynitride layer by rapid thermal oxidation; forming a high-k gate dielectric layer on the ultra-thin interfacial oxide layer by physical vapor deposition; performing a rapid thermal annealing after the deposition of the high-k; depositing a metal nitride gate by physical vapor deposition; doping the metal nitride gate by ion implantation with P-type dopants for a PMOS device, and with N-type dopants for an NMOS device, with a photoresist layer as a mask; depositing a polysilicon layer and a hard mask by a low pressure CVD process, and then performing photolithography process and etching the hard mask; removing the photoresist, and then etching the polysilicon layer/the metal gate/the high-k dielectric layer sequentially to provide a metal gate stack; forming a first spacer, and performing ion implantation with a low energy

Abstract: There is provided a method for forming a metal interlayer via, comprising: forming a seed layer on a first dielectric layer and a first metal layer embedded in the first dielectric layer; forming a mask pattern on the seed layer to expose a portion of the seed layer covering some of the first metal layer; growing a second metal layer on the exposed portion of the seed layer; removing the mask pattern and a portion of the seed layer carrying the mask pattern to expose side walls of the second metal layer, a portion of the first metal layer and the first dielectric layer; forming an insulating barrier layer on the side walls, the portion of the first metal layer and the first dielectric layer. There is also provided a method for forming a metal interconnection line. Both of them can suppress the occurrence of voids.

Abstract: The present application discloses a method for manufacturing a semiconductor structure, comprising the steps of: a) providing a p-type field effect transistor; b) forming a tensile-stressed layer on the p-type field effect transistor; c) removing a portion of the tensile-stressed layer, so that the remaining portion of the tensile-stressed layer generates compressive stress in the channel of the p-type field effect transistor; and d) performing annealing, so as to achieve the object of memorizing compressive stress in a channel of a transistor and improving the performance of the transistor. The method according to the present invention memorizes the compressive stress in the channel of the transistor by a stress memorization technique, increases mobility of holes, and improves overall performance of the semiconductor structure.

Abstract: A semiconductor device includes: a semiconductor substrate; a SiGe relaxed layer on the semiconductor substrate; an NMOS transistor on the SiGe relaxed layer; and a PMOS transistor on the SiGe relaxed layer, in which the NMOS transistor includes a tensile strained epitaxial layer located on the SiGe relaxed layer or embedded in the SiGe relaxed layer; and the PMOS transistor includes a compressive strained epitaxial layer located on the SiGe relaxed layer or embedded in the SiGe relaxed layer. The loss of the strained semiconductor material can be avoided and meanwhile the stress in the channel can be better maintained.

Abstract: The present invention relates to a stress-enhanced transistor and a method for forming the same. The method for forming the transistor according to the present invention comprises the steps of forming a mask layer on a semiconductor substrate on which a gate has been formed, so that the mask layer covers the gate and the semiconductor substrate; patterning the mask layer so as to expose at least a portion of each of a source region and a drain region; amorphorizing the exposed portions of the source region and the drain region; removing the mask layer; and annealing the semiconductor substrate so that a dislocation is formed in the exposed portion of each of the source region and the drain region.

Abstract: A semiconductor device with stress trench isolation and a method for forming the same are provided. The method includes: providing a silicon substrate; forming first trenches and second trenches on the silicon substrate, wherein an extension direction of the first trenches is perpendicular to that of the second trenches; forming a first dielectric layer in the first trenches and forming a second dielectric layer in the second trenches; and forming a gate stack on a portion of the silicon substrate surrounded by the first trenches and the second trenches, wherein a channel length direction under the gate stack is parallel to the extension direction of the first trenches, indices of crystal plane of the silicon substrate are {100}, and the extension direction of the first trenches is along the crystal orientation <110>. The embodiments of the present invention can improve response speed and performance of the devices.

Abstract: A gate stack structure comprises an isolation dielectric layer formed on and embedded into a gate. A sidewall spacer covers opposite side faces of the isolation dielectric layer, and the isolation dielectric layer located on an active region is thicker than the isolation dielectric layer located on a connection region. A method for manufacturing the gate stack structure comprises removing part of the gate in thickness, the thickness of the removed part of the gate on the active region is greater than the thickness of the removed part of the gate on the connection region so as to expose opposite inner walls of the sidewall spacer; forming an isolation dielectric layer on the gate to cover the exposed inner walls. There is also provided a semiconductor device and a method for manufacturing the same. The methods can reduce the possibility of short-circuit occurring between the gate and the second contact hole and can be compatible with the dual-contact-hole process.

Abstract: A hybrid channel semiconductor device and a method for forming the same are provided.

Abstract: The application discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises: a semiconductor substrate comprising a first surface and a second surface opposite to each other; and a silicon via formed through the semiconductor substrate, wherein the silicon via comprises a first via formed through the first surface; and a second via formed through the second surface and electrically connected with the first via, wherein the first and second vias are formed individually. Embodiments of the invention are applicable to the manufacture of a 3D integrated circuit.

Abstract: A semiconductor structure and a method for fabricating the same. A semiconductor structure includes a semiconductor substrate; a channel region formed in the semiconductor substrate; a gate including a dielectric layer and a conductive layer and formed above the channel region; source and drain regions formed at opposing sides of the gate; first shallow trench isolations embedded into the semiconductor substrate and having a length direction parallel to the length direction of the gate; and second shallow trench isolations, each of which abuts the outer sidewall of the source or the drain region and abuts the first shallow trench isolations, in which the source and drain regions include first seed crystal layers abutting the second shallow trench isolations, and the top surfaces of the second shallow trench isolations are higher than or as high as the top surfaces of the source and drain regions.

Abstract: The present invention presents a method for manufacturing a semiconductor device structure as well as the semiconductor device structure. Said method comprises: providing a semiconductor substrate; forming a first insulating layer on the semiconductor substrate; forming a shallow trench isolation embedded in the first insulating layer and the semiconductor substrate; forming a channel region embedded in the semiconductor substrate; and forming a gate stack stripe on the channel region. Said method further comprises, before forming the channel region, performing a source/drain implantation on the semiconductor substrate. By means of forming the source/drain regions in a self-aligned manner before forming the channel region and the gate stack, said method achieves the advantageous effects of the replacement gate process without using a dummy gate, thereby simplifying the process and reducing the cost.

Abstract: The present invention provides a semiconductor device. The semiconductor device comprises contact plugs that comprise a first contact plug formed by a first barrier layer arranged on the source and drain regions and a tungsten layer arranged on the first barrier layer; and second contact plugs comprising a second barrier layer arranged on both of the metal gate and the first contact plug and a conductive layer arranged on the second barrier layer. The conductivity of the conductive layer is higher than that of the tungsten layer. A method for forming the semiconductor device is also provided. The present invention provides the advantage of enhancing the reliability of the device when using the copper contact technique.

Abstract: The present application discloses a semiconductor device comprising a fin of semiconductive material formed from a semiconductor layer over a semiconductor substrate and having two opposing sides perpendicular to the main surface of the semiconductor substrate; a source region and a drain region provided in the semiconductor substrate adjacent to two ends of the fin and being bridged by the fin; a channel region provided at the central portion of the fin; and a stack of gate dielectric and gate conductor provided at one side of the fin, where the gate conductor is isolated from the channel region by the gate dielectric, and wherein the stack of gate dielectric and gate conductor extends away from the one side of the fin in a direction parallel to the main surface of the semiconductor substrate, and insulated from the semiconductor substrate by an insulating layer.

Abstract: A semiconductor device structure and a method for fabricating the same. A method for fabricating semiconductor device structure includes forming gate lines on a semiconductor substrate; forming gate sidewall spacers surrounding the gate lines; forming respective source/drain regions in the semiconductor substrate and on either side of the respective gate lines; forming conductive sidewall spacers surrounding the gate sidewall spacers; and cutting off the gate lines, the gate sidewall spacers and the conductive sidewall spacers at predetermined positions, in which the cut gate lines are electrically isolated gates, and the cut conductive sidewall spacers are electrically isolated lower contacts. The method is applicable to the manufacture of contacts in integrated circuits.

Abstract: The present invention provides a semiconductor device and a method for manufacturing the same. The method includes: providing a substrate; forming a gate stack on the substrate; forming an inter layer dielectric (ILD) to cover the device; etching the ILD at both sides of the gate stack and the substrate below the ILD, so as to form a groove of source and drain regions respectively; depositing a metal diffusion barrier layer in the groove; and filling the groove with a metal to form the source and drain regions. The semiconductor device includes: a substrate; a gate stack on the substrate; an inter layer dielectric (ILD) covering the device; a groove of source and drain regions formed in the ILD at both sides of the gate stack and the substrate below the ILD; and a metal diffusion barrier layer and a metal filler formed in the groove.

Abstract: The present invention relates to the field of semiconductor manufacturing. The present invention provides a method of manufacturing a semiconductor device, which comprises: providing a semiconductor substrate; forming an interface layer, a gate dielectric layer and a gate electrode on the substrate; forming a metal oxygen absorption layer on the gate electrode; performing a thermal annealing process on the semiconductor device so that the metal oxygen absorption layer absorbs oxygen in the interface layer and the thickness of the interface layer is reduced. By means of the present invention, the thickness of the interface layer can be reduced on one hand, and on the other hand the metal in the metal oxygen absorption layer is made to diffuse into the gate electrode and/or the gate dielectric layer through the annealing process, which further achieves the effects of adjusting the effective work function and controlling the threshold voltage.

Abstract: A flash memory device includes a semiconductor substrate, a gate stack formed on the semiconductor substrate; a channel region below the gate stack; spacers outside the gate stack; and source/drain regions outside the channel region and in the semiconductor substrate, in which the gate stack includes a first gate dielectric layer on the channel region; a first conductive layer covering an upper surface of the first gate dielectric layer and inner walls of the spacers; a second gate dielectric layer covering a surface of the first conductive layer; and a second conductive layer covering a surface of the second gate dielectric layer. A method for manufacturing a flash memory device disclosed herein.

Abstract: The present invention provides a body contact device structure and a method for manufacturing the same. According to the present invention, an opening is formed by removing one end of a dummy gate stack after forming the dummy gate stack, wherein a residual portion of the dummy gate stack is a body stack comprising a body pile-up layer that directly contacts a substrate. Next, a replacement gate stack is formed in the opening, and then a body contact is formed on the body pile-up layer in the body stack. The body contact device structure formed by the method of the present invention effectively reduces the parasitic effects and the device area, and improves the performance of the device structure.

Abstract: A semiconductor device comprises a semiconductor substrate on an insulating layer; and a second gate, the second gate is located on the insulating layer and is embedded at least partially in the semiconductor substrate. A method for forming a semiconductor device comprises: forming a semiconductor substrate on an insulating layer; forming a void within the semiconductor substrate, with the insulating layer being exposed by the void; and forming a second gate, with the void being filled with at least one part of the second gate. It facilitates the reduction of the short channel effects, resistances of source and drain regions, and parasitic capacitances.