Abstract: The presented application discloses a capacitor structure and a method for manufacturing the same.

Abstract: The present invention discloses a vertical SOI bipolar junction transistor and a manufacturing method thereof. The bipolar junction transistor includes an SOI substrate from down to up including a body region, a buried oxide layer and a top silicon film; an active region located in the top silicon film formed by STI process; a collector region located in the active region deep close to the buried oxide layer formed by ion implantation; a base region located in the active region deep close to the top silicon film formed by ion implantation; an emitter and a base electrode both located over the base region; a side-wall spacer located around the emitter and the base electrode. The present invention utilizing a simple double poly silicon technology not only can improve the performance of the transistor, but also can reduce the area of the active region in order to increase the integration density.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device has a metal sidewall spacer on the sidewall of a gate electrode on the drain region side. The metal sidewall spacer is made of such metals as Ta, which has an oxygen scavenging effect and can effectively reduce EOT on the drain region side, and thus the ability to control the short channel is effectively increased. In addition, since EOT on the source region side is larger, the carrier mobility of the device will not be degraded. Moreover, such asymmetric device may have a better driving performance.

Abstract: The present invention discloses a semiconductor device. In one embodiment, the semiconductor device comprises a substrate, a diffusion stop layer formed on the substrate, an SOI layer formed on the diffusion stop layer, an MOSFET transistor formed on the SOI layer, and a TSV formed in a manner of penetrating through the substrate, the diffusion stop layer, the SOI layer, and a layer where the MOSFET transistor is located; and an interconnect structure connecting the MOSFET transistor and the TSV.

Abstract: The present invention relates to a semiconductor device. Interface layers of different thickness or different materials are used in the NMOS region and the PMOS region of the semiconductor substrate, which not only effectively reduce EOT of the device, especially EOT of the PMOS device, but also increase the electron mobility of the device, especially the electron mobility of the NMOS device, thereby effectively improving the overall performance of the device.

Abstract: Switches that are actuated through exposure to a magnetic field are described. Such switches include conductive portions that are electrically separate from one another when in an open switch configuration. A mobile element of a switch includes one or more anchoring members that are in electrical contact with one of the conductive portions. The mobile element also has a beam that is attached to the one or more anchoring members. The beam can be attached to the one or more anchoring members by flexures. In some cases, the beam includes a plurality of strips. The beam has an end portion that is configured to move toward the other conductive portion when exposed to an external force, such as a magnetic field. When the mobile element electrically contacts the other conductive portion of the substrate, an electrical pathway is established between the conductive portions, giving rise to a closed switch configuration.

Abstract: A fin transistor structure and a method of fabricating the same are disclosed. In one aspect the method comprises providing a bulk semiconductor substrate, patterning the semiconductor substrate to form a fin with it body directly tied to the semiconductor substrate, patterning the fin so that gaps are formed on the bottom of the fin at source/drain regions of the transistor structure to be formed. This is performed wherein a portion of the fin corresponding to the channel region of the transistor structure to be formed is directly tied to t he semiconductor substrate, while other portions of the fin at the source/drain regions are separated from the surface of the semiconductor substrate by the gaps. Also, filling an insulation material into the gaps, and fabricating the transistor structure based on the semiconductor substrate with the fin formed thereon are disclosed. Thereby, it is possible to reduce the leakage current while maintaining the advantages of body-tied structures.

Abstract: A method for manufacturing a bulk Si nanometer surrounding-gate MOSFET based on a quasi-planar process, including: local oxidation isolation or shallow trench isolation; depositing buffer SiO2 oxide layer/SiN dielectric layer on the bulk Si; electron beam exposure; etching two adjacent slots; depositing SiN sidewalls; isotropically etching Si; dry oxidation; removing SiN by wet etching; forming the nanowire by stress self-constraint oxidation; depositing and anisotropically etching oxide dielectric layer and planarizing surface; releasing the nanowire by wet etching while keeping sufficiently thick SiO2 at bottom as isolation; growing gate dielectric and depositing gate material; etching back the gate and isotropically etching the gate material by using the gate dielectric as a block layer; shallow implantation in the source/drain region; depositing and etching sidewalls; deep implantation in the source/drain region to form contact.

Abstract: A method for manufacturing a bulk Si nanometer surrounding-gate MOSFET based on a quasi-planar process, including: local oxidation isolation or shallow trench isolation; depositing buffer SiO2 oxide layer/SiN dielectric layer on the bulk Si; electron beam exposure; etching two adjacent slots; depositing SiN sidewalls; isotropically etching Si; dry oxidation; removing SiN by wet etching; forming the nanowire by stress self-constraint oxidation; depositing and anisotropically etching oxide dielectric layer and planarizing surface; releasing the nanowire by wet etching while keeping sufficiently thick SiO2 at bottom as isolation; growing gate dielectric and depositing gate material; etching back the gate and isotropically etching the gate material by using the gate dielectric as a block layer; shallow implantation in the source/drain region; depositing and etching sidewalls; deep implantation in the source/drain region to form contact.

Abstract: The present invention proposes a method of forming a dual contact hole, comprising steps of: forming a source/drain region and a replacement gate structure on a semiconductor substrate, the replacement gate structure including a replacement gate; depositing a first inter-layer dielectric layer; planarizing the first inter-layer dielectric layer to expose the replacement gate in the replacement gate structure; removing the replacement gate and depositing to form a metal gate; etching to form a first source/drain contact opening in the first inter-layer dielectric layer; sequentially depositing a liner and filling conductive metal in the first source/drain contact opening to form a first source/drain contact hole; depositing a second inter-layer dielectric layer on the first inter-layer dielectric layer; etching to form a second source/drain contact opening and a gate contact opening in the second inter-layer dielectric layer; and sequentially depositing a liner and filling conductive metal in the second source

Abstract: The invention relates to a method of making an integrated circuit inductor that comprises a silicon substrate and an oxide layer on the silicon substrate. In one aspect, the method comprises depositing an inductive loop on the oxide layer, and making a plurality of apertures in the oxide layer beneath the inductive loop. The method also comprises providing a plurality of bridges adjacent the apertures and provided by portions of the oxide layer between an inner region within the inductive loop and an outer region of the oxide layer without the inductive loop, the inductive loop being supported on the bridges. The method comprises forming a trench in the silicon substrate beneath the bridges, to provide an air gap between the inductive loop and the silicon substrate.

Abstract: A feedback image rejection downconversion system is described, which can be used in low IF receivers with good performance and completely integrated. In the forward path of the system, quadrature mixers and complex filters are used for frequency downconversion and separation of the RF signal from the image signal. In the feedback path, a correlator, a gain mismatch estimator and two VGAs have been used to detect, estimate and compensate the amplitude and phase mismatch between the forward I and Q path signals. The whole system is self-tuned and can operate in both closed and open loop mode. A very high and robust image rejection ratio (over 60 dB) has been achieved.

Abstract: Method of fabricating a micro-mirror switching device in single crystal silicon are described. The device is fabricated as three main elements: silicon mirror plate with metal-mirror, secondary actuator, and hinge/spring mechanism to integrate the mirror plate with the actuator. p-n junction is first formed on p-type silicon. Trenches are then etched in n-silicon to define the device element boundaries and filled with silicon dioxide. Three layers of sacrificial oxide and two structural poly-silicon layers are deposited and patterned to form device elements. Novel release processes, consisting of backside electrochemical etching in potassium-hydroxide, reactive ion etching to expose oxide-filled trenches from the bottom, and hydrofluoric acid etching of sacrificial oxide layers and oxide in silicon trenches, form the silicon blocks; those that are not attached to structural poly-silicon are sacrificed and those that are attached are left in place to hold together the switching device elements.

Abstract: When using hot alkaline etchants such as KOH, the wafer front side, where various devices and/or circuits are located, must be isolated from any contact with the etchant. This has been achieved by using two chambers that are separated from each other by the wafer that is to be etched. Etching solution in one chamber is in contact with the wafer's back surface while deionized water in the other chamber contacts the front surface. The relative liquid pressures in the chambers is arranged to be slightly higher in the chamber of the front surface so that leakage of etchant through a pin hole from back surface to front surface does not occur. As a further precaution, a monitor to detect the etchant is located in the DI water so that, if need be, etching can be terminated before irreparable damage is done.

Abstract: A method for spin coating a polymeric material film upon a wafer rotatably mounted within a spin coater; the wafer having a surface, including the following steps. A first step of rotating the wafer on an axis perpendicular to the wafer surface while applying a predetermined amount of polymeric material while rotating the wafer at a rotational speed of from about 300 to 1200 rpm for from about 2.5 to 5 seconds to spread the polymeric material on the whole surface of the wafer. A second step of increasing the rotational speed of the wafer to about 5500 rpm for about 2.5 seconds. A third step of decreasing the rotational speed of the wafer to about 300 to 1200 rpm for about 2.5 seconds. A fourth step of increasing the rotational speed of the wafer to about 5500 rpm for about 20 seconds to form the polymeric material film having a predetermined thickness over the whole surface of the wafer.

Abstract: A method for forming wafers having through-wafer vias for wafer-level packaging of devices, the method comprising the steps of depositing metal on one of two wafers; bonding the two wafers using the metal deposited on the one of the two wafers; forming a through-wafer via in one of the two wafers; filling the through-wafer via with a conductive material; and forming a cavity in the one of the two wafers having the through-wafer via wherein the cavity is superposable over a device.

Abstract: A MOSFET device in strained silicon-on-SiGe and a method of forming the device are described. The said device achieves reduced junction leakage due to the lower band-gap values of SiGe. The method consists of forming isolation trenches in a composite strained-Si/SiGe substrate and growing a liner oxide by wet oxidation such that oxidation is selective to SiGe only, with negligible oxidation of silicon surfaces. Selective oxidation results in oxide encroachment under strained-Si, thereby reducing the junction area after device fabrication is completed. Reduced junction area leads to reduced n+/p or p+/n junction leakage current.

Abstract: A process to form a capillary that is well insulated from its environment is described. Said process has two stages. The first stage, which is the same for both of the invention's two embodiments, comprises forming a micro-channel in the surface of a sheet of glassy material. For the first embodiment, this sheet is bonded to a layer of oxide, that lies on the surface of a sheet of silicon, thereby sealing in the capillary. After all silicon has been selectively removed, a thin membrane of oxide remains. Using a low temperature bonding process, a second sheet of glassy material is then bonded to this membrane. In the second embodiment, the silicon is not fully removed. Instead, the oxide layer of the first embodiment is replaced by an oxide/nitride/oxide trilayer which provides improved electrical insulation between the capillary and the remaining silicon at a lower level of inter-layer stress.

Abstract: An improved method of forming a dual damascene structure that includes an organosilicate glass (OSG) dielectric layer is described. A via first process is followed in which a via is formed in the OSG layer and preferably stops on a SiC layer. The SiC layer is removed prior to stripping a photoresist containing the via pattern. A planarizing BARC layer is formed in the via to protect the exposed substrate from damage during trench formation. The method provides higher Kelvin via and via chain yields. Damage to the OSG layer at top comers of the via and trench is avoided. Furthermore, there is no pitting in the OSG layer at the trench bottom. Vertical sidewalls are achieved in the via and trench openings and via CD is maintained. The OSG loss during etching is minimized by removing the etch stop layer at an early stage of the dual damascene sequence.

Abstract: Electrostatic discharge (ESD) protection for circuits which utilize multiple power supply rails, both positive (Vdd) and negative (Vss). Vdd busses remain completely isolated, while Vss busses are joined by pairs of complementary polarity diodes (made typically with P+/N-well diodes in an N/P-substrate process) thus keeping Vss busses isolated from each other. The I/O diodes of high frequency I/O pads are arranged in a square layout to achieve the best current/capacitance ratio. Each pair of power rails is provided with its own power shunt circuit, placing each shunt in physical proximity to the I/O pad it must protect. Shunts are designed to clamp at a very low voltage during an ESD event using mostly PMOS transistors. The protection circuit is laid out such that the worst case ESD event will flow at most between two I/O pads and one power shunt.