Abstract: A new inductor-capacitor resonance RF (LCR-RF) switching device is achieved. The device comprises a microelectronic mechanical switch and a spiral inductor. The microelectronic mechanical switch comprises, first, a first dielectric layer overlying a substrate. A down electrode overlies the first dielectric layer. A second dielectric layer overlies the down electrode. An up electrode overlies the down electrode with the second dielectric layer therebetween. A bridge post overlies the first dielectric layer and does not contact the down electrode or the up electrode. Multiple bridge posts may be used. Finally, a membrane is suspended over said down electrode. One end of the membrane is fixed to the top of the bridge post. An electrostatic potential between the membrane and the down electrode will cause the membrane to flex down toward the down electrode. This flexing of the membrane will cause the capacitance of the switching device to vary.

Abstract: The present invention significantly reduces charging effects in electrostatic devices due to charge accumulation in or on the insulating materials on the active surfaces of the devices. This has been achieved by replacing the dielectric material that is normally present between the force generating conductor surfaces with a semi-insulating material. This semi-insulating film overcomes the effects of charging, while avoiding short-circuits when the surfaces are pulled into contact. It is not subject to insulation breakdown within the range of voltages used to operate the device. Examples of semi-insulating materials that may be used are semi-insulating polysilicon (SIPOS) and silicon rich silicon nitride.

Abstract: Method and apparatus for etching a tapered trench in a layer of material with a highly controllable wall profile. The layer of material has a mask adjacent a surface thereof having an opening which defines a location on the layer of material at which the trench is to be formed. Vertical etch process steps and opening enlarging process steps are then performed in an alternating manner until the trench has been etched to a desired depth. The method permits very deep tapered trenches of up to 80-100 um or more to be formed in a silicon substrate or other layer of material in a highly controllable manner. The method can be incorporated into processes for manufacturing numerous devices including MEMS devices and high power RF devices such as LDMOS and VDMOS devices.

Abstract: A novel silicon RF LDMOSFET structure based on the use of a stacked LDD, is disclosed. The LDD has been modified from a single layer of N type material to a stack of three layers. These are upper and lower N type layers with a P type layer between them. The upper N type layer is heavily doped to reduce the on-resistance of the device, while the lower N type layer is lightly doped to reduce the output capacitance, thereby improving the high frequency performance. The middle P layer is heavily doped which allows it to bring about pinch-off of the two N layers, thereby raising the device's breakdown voltage. A process for manufacturing the device, as well as experimental data concerning its performance are also given.

Abstract: A method for forming bonds between similar and dissimilar material surfaces, particularly the surfaces of silicon wafers having various devices disposed thereon, wherein such bonds can be formed at room temperature and do not require the application of high pressures or voltages. The bonding material is polydimethylsiloxane, which is transparent and bio-compatible.

Abstract: A new inductor-capacitor resonance RF (LCR-RF) switching device is achieved. The device comprises a microelectronic mechanical switch and a spiral inductor. The microelectronic mechanical switch comprises, first, a first dielectric layer overlying a substrate. A down electrode overlies the first dielectric layer. A second dielectric layer overlies the down electrode. An up electrode overlies the down electrode with the second dielectric layer therebetween. A bridge post overlies the first dielectric layer and does not contact the down electrode or the up electrode. Multiple bridge posts may be used. Finally, a membrane is suspended over said down electrode. One end of the membrane is fixed to the top of the bridge post. An electrostatic potential between the membrane and the down electrode will cause the membrane to flex down toward the down electrode. This flexing of the membrane will cause the capacitance of the switching device to vary.

Abstract: An interconnect line on an IMD layer on a semiconductor device is formed in an interconnect hole in the IMD layer. The interconnect hole has walls and a bottom in the IMD layer. A diffusion barrier is formed on the walls and the bottom of the hole. Fill the interconnect hole with a copper metal line. Perform a CMP step to planarize the device and to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole. Alternatively, a blanket deposit of a copper metal line layer covers the diffusion layer and fills the interconnect hole with a copper metal line. Perform a CMP process to planarize the device to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole in a self-aligned deposition process.

Abstract: In the prior art LDMOSFET devices capable of handling high power have been made by locating the source contact on the bottom surface of the device, allowing for good heat sinking, with connection to the source region being made through a sinker. However, this structure has poor high frequency characteristics. Also in the prior art, good high frequency performance has been achieved by introducing a dielectric layer immediately below the source/drain regions (SOI) but this structure has poor handling capabilities. The present invention achieves both good high frequency behavior as well as good power capability in the same device. Instead of inserting a dielectric layer over the entire cross-section of the device, the dielectric layer is limited to being below the heavily doped section of the drain with a small amount of overlap into the lightly doped section. The structure is described in detail together with a process for manufacturing it.

Abstract: A process has been described which makes use of polysilicon beam as the structural material instead of single crystal silicon for the fabrication of MEMS sensors/actuators. The invention describes the process for fabricating suspended polysilicon beams by using deep trenches etched into silicon substrate as a kind of a mould to form polysilicon beams. The polysilicon beams are subsequently released by isotropically etching away the silicon surrounding the polysilicon beams. This results in free standing polysilicon members, which form the MEMS structures. In addition to the general process, three approaches to making electrical contact to the beams are presented.

Abstract: The invention describes a thermal cycler which permits simultaneous treatment of multiple individual samples in independent thermal protocols, so as to implement large numbers of DNA experiments simultaneously in a short time. The chamber is thermally isolated from its surroundings, heat flow in and out of the unit being limited to one or two specific heat transfer areas. All heating elements are located within these transfer areas and at least one temperature sensor per heating element is positioned close by. Fluid bearing channels that facilitate sending fluid into, and removing fluid from, the chamber are provided. The chambers may be manufactured as integrated arrays to form units in which each cycler chamber has independent temperature and fluid flow control. Two embodiments of the invention are described together with a process for manufacturing them.

Abstract: The current invention teaches the use of e-beam patterning techniques for forming contact and via holes of diameter less than about 0.15 microns down to 0.05 microns. E-beam lithography has higher resolution (down to 30-50 nanometers) as compared to 130-150 nanometer when using deep ultra violet (DUV) photolithography patterning techniques. In addition the invention uses a mix and match approach by employing a conventional I-line, or deep UV, resist to form the trench pattern and e-beam lithography tools to form the contact and vial hole patterns. A simplified process scheme is developed where contact/via holes are formed first on solvent developable e-beam resist and the trench pattern is formed on aqueous developable photoresist coated on top of the e-beam resist.

Abstract: A buffer amplifier comprising a source follower-common drain circuit with a feedback path from the output of the drain follower to the input gate of the source follower. The feedback circuit is designed such that the output of the drain follower can be guaranteed to be at a voltage midway between the positive and the negative voltage supply of the circuit. This is the optimum operating point since it allows the largest signal swing. A small transconductance is realized by biasing the transistors of the feedback amplifier with very low currents; preferably by operating them in their weak inversion region. Feedback through the feedback amplifier is only present at DC (direct current) and at very low frequencies. This stabilizes the DC voltage at the drain of the common drain transistor, which, via an output capacitor, is also the output of the buffer amplifier.

Abstract: An image enhancement technique for use, for example in infrared or photoemission microscopy, comprises obtaining an in-focus image of the sample and an out of focus image achieved by relative movement of the sample and the microscope, and subtracting the out of focus image from the in-focus image. As a result the low frequency components are subtracted out, together with the lens and focal plane array aberrations, providing an enhanced resultant image. Because of the high levels of magnification, only small movement is required to obtain the out of focus image, allowing an enhanced image to be obtained in real time.

Abstract: The invention describes a thermal cycler which permits simultaneous treatment of multiple individual samples in independent thermal protocols, so as to implement large numbers of DNA experiments simultaneously in a short time. The chamber is thermally isolated from its surroundings, heat flow in and out of the unit being limited to one or two specific heat transfer areas. All heating elements are located within these transfer areas and at least one temperature sensor per heating element is positioned close by. Fluid bearing channels that facilitate sending fluid into, and removing fluid from, the chamber are provided. The chambers may be manufactured as integrated arrays to form units in which each cycler chamber has independent temperature and fluid flow control. Two embodiments of the invention are described together with a process for manufacturing them.

Abstract: A method of forming interconnect structures in a semiconductor device, comprising the following steps. A semiconductor structure is provided. In the first embodiment, at least one metal line is formed over the semiconductor structure. A silicon-rich carbide barrier layer is formed over the metal line and semiconductor structure. Finally, a dielectric layer, that may be fluorinated, is formed over the silicon-rich carbide layer. In the second embodiment, at least one fluorinated dielectric layer, that may be fluorinated, is formed over the semiconductor structure. The dielectric layer is patterned to form an opening therein. A silicon-rich carbide barrier layer is formed within the opening. A metallization layer is deposited over the structure, filling the silicon-rich carbide barrier layer lined opening. Finally, the metallization layer may be planarized to form a planarized metal structure within the silicon-rich carbide barrier layer lined opening.

Abstract: A method of forming a boron carbide layer for use as a barrier and an etch-stop layer in a copper dual damascene structure, and the structure itself are disclosed. In addition to providing a good barrier to copper diffusion, good insulating properties, high etch selectivity with respect to dielectric insulators, boron carbide also provides good electrical characteristics because of its low dielectric constant of less than 5. The amorphous boron carbide is formed in a PECVD chamber by introducing a boron source gas such as B2H6, B5H9+, and carbon source gas such as CH4 and C2H6 at a deposition temperature of about 400° C. Any one, or any combination of the passivation, etch-stop, cap layers of the damascene structure can comprise boron carbide.

Abstract: A plastic ball grid array package is designed to pass the JEDEC Level 1 Moisture Sensitivity Test (the “popcorn test”). The plastic ball grid array design minimizes contact between a mold compound/encapsulate/glob top and metal surfaces. The present plastic ball grid array design maximizes contact between the mold compound/encapsulate/glob top and either the laminate core or the solder resist in order to take advantage of this strong bond which will help disable delamination. Furthermore, solder resistive material overlaps the interface between metal surfaces and the laminate core.

Abstract: A method of etching trenches through a low-k material layer using a hard mask wherein the trenches are sized down from the mask size by etching without sacrificing a vertical trench profile is described. A low-k dielectric material is provided over a region to be contacted on a substrate. A hard mask layer is deposited overlying the dielectric material. A mask is formed over the hard mask layer wherein the mask has a first opening of a first width. A second opening is etched in the hard mask layer where it is exposed by the mask wherein the second opening has a second width smaller than the first width and wherein the second opening has inwardly sloping sidewalls. A trench is etched through the dielectric layer to the region to be contacted through the second opening whereby the trench has a width equal to the second width. The trench is filled with a metal layer to complete fabrication of the integrated circuit device.

Abstract: A bipolar complementary metal oxide semiconductor device has a c-well fabricated using profile engineering (a multi-energy implant using accurate dosages and energies determined by advance simulation) to provide a higher c-well implant dose while creating a narrow region with relatively low concentration in the collector depletion range to avoid low base-collector breakdown. This achieves a much lower collector series resistance to pull-up a frequency response, a collector sheet resistance which can be as low as 150 &OHgr;/sq., and fT may be increased to 20 GHz or higher.

Abstract: An apparatus is provided in a digital communications device for efficiently determining the Hamming distance for trellis based decoders, such as decoders for punctured convolutional codes. The Hamming distance is pre-determined for all codes and stored in program memory. In one version, the device comprises five components including a state sequencing circuit, a Hamming distance table generator, a Hamming distance table, a Hamming distance retrieval circuit, and an ACS circuit. The state sequencer groups all of the possible 2m possible states into groups of similar branch metrics. The Hamming distance table generator is responsive to the state sequencer and determines the Hamming distance for all combinations of puncture code, received symbol, and transition paths. This may be performed once and stored in permanent memory or performed each time the digital communications device is initialized and stored in a random access memory.