Abstract: A temperature compensating biasing circuit is constructed by first determining a piecewise function substantially describing a required bias current with respect to temperature. Reference signals are created such that each reference signal describes an amount of contributing currents that, when summed together, generate a master biasing current. The biasing current generator is further constructed to create a thermal signal indicating an operating temperature. Each of the reference signals is compared to the thermal signal. The biasing current generator then identifies which of the contributing currents or portions of the contributing currents are being included to generate the master biasing current. The identified contributing currents and the portions of the contributing currents are then summed to form the master biasing current. The master biasing current may be mirrored to form bias currents that have the temperature compensation bias function.

Abstract: A process for manufacturing a buried oxide layer for use in partial SOI structures is described. The process begins with the etching of deep trenches into a silicon body. For a preselected depth below the surface, the inner walls of the trenches are protected and oxidation of said walls is then effected until pinch-off occurs, both inside the trenches and in the material between trenches. The result is a continuous layer of wade whose size and shape are determined by the number and location of the trenches. Application of the process to the manufacture of a partial SOI RFLDMOS structure is also described together with performance data for the resulting device.

Abstract: A high frequency differential amplifier with a circuit topology which ensures that bias currents of the high transconductance differential transistors with minimum channel length are exactly equal, i.e., each differential transistor carries exactly half of the total current I0 of the differential amplifier. This is achieved by coupling each differential transistor via its own current source to the reference potential. To insure a good match between the current sources, the current source devices are made with long channel lengths. Impedances are coupled between the junctions of each differential transistor pair and its current source to insure good AC gain. For the variable gain differential amplifier the spread in the gain control characteristics is reduced by making the aspect ratio of the first pair of differential transistors larger than that of the second pair of differential transistors.

Abstract: The present invention is directed to a method for the lamination of fluoropolymers to the surfaces of metals, and especially to copper, gold, and platinum, and to printed circuit board (PCB) substrate at temperatures substantially below the sintering temperatures or melting temperatures of the fluoropolymers. More specifically, the invention is directed to a method for surface modification of fluoropolymers by thermal graft copolymerization with concurrent lamination of metals in the presence of a functional monomer and an adhesive such as an epoxy resin. The process can be carried out under atmospheric conditions and in the complete absence of an added polymerization initiator. The laminated fluoropolymer-metal or fluoropolymer-PCB substrate interfaces exhibit T-peel strengths of no less than 8 N/cm. This invention can also be applied to substantially improve the adhesion between PCB substrates and metals.

Abstract: The present invention is directed to a method for the lamination of metals, and especially copper, to the surface of polyimides and derivatives of polyimides at temperatures substantially below the curing temperature of the imide polymers. More specifically, the invention is directed to a method for surface modification of polyimides and derivatives of polyimides by thermal graft copolymerization and interfacial polymerization with concurrent lamination of the metal of interest in the presence of an appropriate functional monomer. The process can be carried out under atmospheric conditions and either in the presence or the complete absence of an added polymerization initiator. The so laminated polyimide-metal interfaces exhibit T-peel adhesion strengths in excess of 16 N/cm. The adhesion strength also exceeds the fracture strength of polyimide films with a thickness of 75 &mgr;m.

Abstract: A method for making low sheet resistance local metal interconnections and improved transistor performance is described. The method involves patterning a polysilicon layer and a silicon nitride (Si3N4) cap layer over device areas to form FET gate electrodes, and the patterned polysilicon extends over the field oxide regions to form portions of the local interconnections. After forming source/drain areas and sidewall spacers on the FET gate electrodes, a silicon oxide (SiO2) insulating layer is deposited and polished back to the Si3N4 cap. The Si3N4 is then selectively removed over the patterned polysilicon layer, leaving recesses in the SiO2 layer. After etching contact openings in the SiO2 layer to the substrate, a high electrically conducting metal layer, having a barrier layer, is deposited and patterned to complete the local interconnections.

Abstract: A method of integrated circuit component integration in copper interconnects, including the following steps of the first embodiment. A wafer is provided having an exposed top-most planar copper interconnect. The wafer being divided into one or more areas selected from the group consisting of: a spiral inductor area having an exposed planar copper interconnect bottom half of a stacked spiral inductor; a MIM capacitor area having an exposed planar copper interconnect bottom plate and an exposed planar copper interconnect contact point of a MIM capacitor; and a precision resistor area having a two exposed planar copper interconnect routing points of a precision resistor. A spiral inductor is formed within the spiral inductor area; a MIM capacitor is formed within the MIM capacitor area; and a precision resistor is formed within the precision resistor area.

Abstract: A gain compensation circuit that compensates for variations in gain of a high gain, high frequency amplifier due to changes in mobility of transistor and resistor components of the amplifier. The gain compensation circuit includes a current adjustment circuit and a gain factor evaluation circuit. The current adjustment circuit modifies a bias current provided to each amplifier stage of a plurality of amplifier stages that make up the high gain, high frequency amplifier. The modification of the bias current adjusts the gain factor of the amplifier. The gain factor evaluation circuit is in communication with the current adjustment circuit to determine changes in the gain factor of the high gain, high frequency amplifier. From the determination, the gain factor evaluation circuit provides a compensation signal to the current adjustment circuit indicating a modification factor for the biasing current for each amplifier stage.

Abstract: Electrostatic discharge (ESD) protection for circuits which utilize multiple power supply rails, both positive (Vdd) and negative (Vss). Vdd busses remain completely isolated, while Vss busses are joined by pairs of complementary polarity diodes (made typically with P+/N-well diodes in an N/P-substrate process) thus keeping Vss busses isolated from each other. The I/O diodes of high frequency I/O pads are arranged in a square layout to achieve the best current/capacitance ratio. Each pair of power rails is provided with its own power shunt circuit, placing each shunt in physical proximity to the I/O pad it must protect. Shunts are designed to clamp at a very low voltage during an ESD event using mostly PMOS transistors. The protection circuit is laid out such that the worst case ESD event will flow at most between two I/O pads and one power shunt.

Abstract: A process for manufacturing a buried oxide layer for use in partial SOI structures is described. The process begins with the etching of deep tenches into a silicon body. For a preselected depth below the surface, the inner walls of the trenches are protected and oxidation of said walls is then effected until pinch-off occurs, both inside the trenches and in the material between trenches. The result is a continuous layer of oxide whose size and shape are determined by the number and location of the trenches.

Abstract: The invention describes a thermal cycler which permits simultaneous treatment of multiple individual samples in independent thermal protocols, so as to implement large numbers of DNA experiments simultaneously in a short time. The chamber is thermally isolated from its surroundings, heat flow in and out of the unit being limited to one or two specific heat transfer areas. All heating elements are located within these transfer areas and at least one temperature sensor per heating element is positioned close by. Fluid bearing channels that facilitate sending fluid into, and removing fluid from, the chamber are provided. The chambers may be manufactured as integrated arrays to form units in which each cycler chamber has independent temperature and fluid flow control. Two embodiments of the invention are described together with a process for manufacturing them.

Abstract: The invention describes a thermal cycler which permits simultaneous treatment of multiple individual samples in independent thermal protocols, so as to implement large numbers of DNA experiments simultaneously in a short time. The chamber is thermally isolated from its surroundings, heat flow in and out of the unit being limited to one or two specific heat transfer areas. All heating elements are located within these transfer areas and at least one temperature sensor per heating element is positioned close by. Fluid bearing channels that facilitate sending fluid into, and removing fluid from, the chamber are provided. The chambers may be manufactured as integrated arrays to form units in which each cycler chamber has independent temperature and fluid flow control. Two embodiments of the invention are described together with a process for manufacturing them as well as two schemes for making connections to the outside world.

Abstract: It is often desirable to be able to perform an array of micro-chemical reactions simultaneously but with each reaction proceeding at a different temperature and/or for a different time. A classic example is the polymerase chain reaction associated with DNA analysis. In the present invention, this is achieved by means of an apparatus made up of a chip of plastic, or similar low cost material, containing an array of reaction chambers. After all chambers have been filled with reagents, the chip is pressed up against a substrate, typically a printed circuit board, there being a set of temperature balancing blocks between the chip and the substrate. Individually controlled heaters and sensors located between the blocks and the substrate allow each chamber to follow its own individual thermal protocol while being well thermally isolated from all other chambers and the substrate. The latter rests on a large heat sink to avoid temperature drift over time. A process for manufacturing the apparatus is also disclosed.

Abstract: A method of forming bonds between similar and dissimilar material surfaces particularly the surfaces of silicon wafers having various devices disposes thereon, wherein such bonds can be formed at room temperature and do not require the application of high pressures or voltages. The bonding material is polydimethylsiloxane, which is transparent and bio-compatible.

Abstract: A method of integrated circuit component integration in copper interconnects, including the following steps of the first embodiment. A wafer is provided having an exposed top-most planar copper interconnect. The wafer being divided into one or more areas selected from the group consisting of: a spiral inductor area having an exposed planar copper interconnect bottom half of a stacked spiral inductor; a MIM capacitor area having an exposed planar copper interconnect bottom plate and an exposed planar copper interconnect contact point of a MIM capacitor; and a precision resistor area having a two exposed planar copper interconnect routing points of a precision resistor. A spiral inductor is formed within the spiral inductor area; a MIM capacitor is formed within the MIM capacitor area; and a precision resistor is formed within the precision resistor area.

Abstract: In the prior art LDMOSFET devices capable of handling high power have been made by locating the source contact on the bottom surface of the device, allowing for good heat sinking, with connection to the source region being made through a sinker. However, this structure has poor high frequency characteristics. Also in the prior art, good high frequency performance has been achieved by introducing a dielectric layer immediately below the source/drain regions (SOI) but this structure has poor power handling capabilities. The present invention achieves both good high frequency behavior as well as good power capability in the same device. Instead of inserting a dielectric layer over the entire cross-section of the device, the dielectric layer is limited to being below the heavily doped section of the drain with a small amount of overlap into the lightly doped section. The structure is described in detail together with a process for manufacturing it.

Abstract: An inductor has a spiral aluminum track deposited on an oxide layer over a silicon substrate. The substrate is etched away to form a trench, which extends around beneath the track and provides an air gap having a low dielectric constant. The oxide layer has an inner region within the track, an outer region outside the track and a bridging region extending between the other regions. The bridging region is comprised of intact bridges and gaps therebetween, which are open to the trench and through which an etchant has access to the silicon substrate to form the trench by etching.

Abstract: A novel silicon RF LDMOSFET structure based on the use of a stacked LDD, is disclosed. The LDD has been modified from a single layer of N type material to a stack of three layers. These are upper and lower N type layers with a P type layer between them. The upper N type layer is heavily doped to reduce the on-resistance of the device, while the lower N type layer is lightly doped to reduce the output capacitance, thereby improving the high frequency performance. The middle P layer is heavily doped which allows it to bring about pinch-off of the two N layers, thereby raising the device's breakdown voltage. A process for manufacturing the device, as well as experimental data concerning its performance are also given.

Abstract: A wide-band single-ended to differential converter (DC to 1 GHz) with very low amplitude and phase matching errors, of the order of 0.01 dB and 0.15 degrees respectively and using CMOS technology, is comprised of a first and a second stage. The very low amplitude and phase matching errors have been achieved firstly by the use of capacitive means CD across the gate and source of the first stage MOS transistor M1 with a value equal to the drain to ground (reference potential) parasitic capacitance of the tail current source device for the first stage, and secondly by using equal valued capacitive means CF1, CF2 in the second stage and setting their values to be several (5-10) times more than the gate-drain parasitic capacitances of either of the differential transistors of the second stage.

Abstract: A new method of fabricating solder bumps in the manufacture of an integrated circuit device has been achieved. Contact pads are provided overlying a semiconductor substrate. A passivation layer is provided overlying the contact pads. The passivation layer has openings that expose a top surface of the contact pads. A sacrificial layer is deposited overlying the passivation layer and the exposed top surface of the contact pads. The sacrificial layer is not wettable to solder. Under bump metallurgy (UBM) caps may be formed either by deposition and patterning of a UBM layer stack or by selective electroless deposition of a material such as nickel and gold. An aperture mask is formed overlying the sacrificial layer. The aperture mask has openings that expose a part of the sacrificial layer overlying the contact pads. A solder layer is printed into the openings in the aperture mask. The solder layer is reflowed to form solder bumps overlying the contact pads. The aperture mask is stripped away.