Abstract: A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes: line type bits configured to store an indication that a corresponding cache line of the second sub-cache is configured to store write-miss data, and an eviction controller configured to evict a cache line of the second sub-cache storing write-miss data based on an indication that the cache line has been fully written.

Abstract: An integrated circuit (IC) includes a lower group III-N layer having a first composition over a substrate, and an upper group III-N layer having a different second composition over the lower group III-N layer. A gate electrode of a High Electron Mobility Transistor (HEMT) is located over the upper group III-N layer. First and second resistor contacts make a conductive connection to the lower group III-N layer. An unbiased group III-N cover layer is located on the upper group III-N layer in a resistor area including a high Rs 2-DEG resistor, where the unbiased group III-N cover layer is positioned between the first and second contacts.

Abstract: A method includes receiving, by a MMU for a processor core, an address translation request from the processor core and providing the address translation request to a TLB of the MMU; generating, by matching logic of the TLB, an address transaction that indicates whether a virtual address specified by the address translation request hits the TLB; providing the address transaction to a general purpose transaction buffer; and receiving, by the MMU, an address invalidation request from the processor core and providing the address invalidation request to the TLB. The method also includes, responsive to a virtual address specified by the address invalidation request hitting the TLB, generating, by the matching logic, an invalidation match transaction and providing the invalidation match transaction to one of the general purpose transaction buffer or a dedicated invalidation buffer.

Abstract: A motor controller that is operable to control a motor includes drive current generation circuitry having an output coupled to the motor. The motor controller further includes a velocity control path. The velocity control path includes angular velocity estimation circuitry having an input adapted to be coupled to the motor, a velocity comparator having first input coupled to a target velocity input and a second input coupled to an output of the angular velocity estimation circuitry, and an adaptive velocity controller having a first input coupled to an output of the velocity comparator and having an output coupled to a first input of the drive current generation circuitry. The motor controller further includes controller parameter determination circuitry having a first input coupled to the output of the angular velocity estimation circuitry and having an output coupled to a second input of the adaptive velocity controller.

Abstract: An IC includes first-third power rails over a semiconductor substrate. The first rail has a first polarity different from the second and third rails. The IC includes multiple first cells on the semiconductor substrate in first and second rows. The first row is separated from the second row by the first power rail. Each first cell includes a first height and a first structure having at least one transistor. For each first cell in the first row, the first structure is entirely between the first and second rails. Further, for each first cell in the second row, the first structure is between the first and third rails. The IC includes an extension cell arranged on the semiconductor substrate in the first row. The extension cell includes a second structure having at least one transistor. A portion of the second structure extends into the second row.

Abstract: A system and method for phase and gain calibration of a current sensor system. The system comprises a microcontroller configured to execute software in an energy measurement component and a calibration computer having a calibration application. The energy measurement component receives first and second digital signals representing current and voltage signals, respectively, received from a test source, and calculates active power and a power factor, and provides those values to the calibration computer. The power factor is converted to a converted phase angle. Based on the information received from the energy measurement component, the calibration application calculates parameters used to update components within the microcontroller to maximize the accuracy of the current sensor system.

Abstract: A device includes a first bit cell, a second bit cell, and a multiply and average (MAV) circuit. The MAV circuit includes a first selection circuit and a second selection circuit. The first selection circuit has a first selection input and coupled to first and second capacitor terminals, and the first selection circuit is configured to, responsive to a state of the first selection input, set respective states of the first and second capacitor terminals based on a state of the first bit cell. The second selection circuit has a second selection input and is coupled to the first and second capacitor terminals. The second selection circuit is configured to, responsive to a state of the second selection input, set the respective states of the first and second capacitor terminals based on a state of the second bit cell.

Abstract: An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric sidewalls having a deep n-type diffusion (DEEPN diffusion) ring (DEEPN ring) contacting the dielectric sidewall extending downward to the NBL. The DEEPN ring defines an enclosed p-epi region. A plurality of inner DT structures are within the enclosed p-epi region having dielectric sidewalls and DEEPN diffusions contacting the dielectric sidewalls extending downward from the topside surface to the NBL. The inner DT structures have a sufficiently small spacing with one another so that adjacent DEEPN diffusion regions overlap to form continuous wall of n-type material extending from a first side to a second side of the outer DT ring dividing the enclosed p-epi region into a first and second p-epi region. The first and second p-epi region are connected by the NBL.

Abstract: Software instructions are executed on a processor within a computer system to configure a streaming engine with stream parameters to define a multidimensional array. The stream parameters define a size for each dimension of the multidimensional array and a pad value indicator. Data is fetched from a memory coupled to the streaming engine responsive to the stream parameters. A stream of vectors is formed for the multidimensional array responsive to the stream parameters from the data fetched from memory. A padded stream vector is formed that includes a specified pad value without accessing the pad value from system memory.

Abstract: A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.

Abstract: In described examples, an integrated circuit includes first, second, third, and fourth image processing blocks, a data selection circuitry, and a pipeline memory. An input of the first image processing block receives raw image data. An input of the second image processing block is coupled to an output of the first image processing block. An input of the third image processing block is coupled to an output of the second image processing block. A first input of the data selection circuitry is coupled to an output of the first image processing block, and a second input of the data selection circuitry is coupled to an output of the second image processing block. A data input of the pipeline memory is coupled to an output of the data selection circuitry, and an output of the pipeline memory is coupled to an input of the fourth image processing block.

Abstract: An example analog-to-digital converter (ADC) comprising: sample and hold circuitry coupled to an analog input; a first sub-ADC coupled to the sample and hold circuitry; a multiplying digital-to-analog converter (M-DAC) coupled to the first sub-ADC; summation circuitry coupled to the sample and hold circuitry and the M-DAC; an amplifier coupled to the summation circuitry; a second sub-ADC coupled to the amplifier; and reference generation circuitry coupled to the first sub-ADC, the M-DAC, and the second sub-ADC, the reference generation circuitry including: reference voltage circuitry coupled to the M-DAC; a first resistor coupled to the reference voltage circuitry; a second resistor coupled to the first resistor; and a capacitor coupled in parallel to the second resistor by a switch.

Abstract: In described examples, a memory system is accessed by reading a data line and error detection bits for the data line from a first memory. The data line and the error detection bits from the first memory are decoded to determine if an error is present in the data line from the first memory. A copy of the data line and the error detection bits are stored in a second memory. The copy of the data line and error detection bits are read from the second memory. The copy of the data line and error detection bits are decoded to determine if an error is present in the copy of the data line from the second memory.

Abstract: A system to implement debugging for a multi-threaded processor is provided. The system includes a hardware thread scheduler configured to schedule processing of data, and a plurality of schedulers, each configured to schedule a given pipeline for processing instructions. The system further includes a debug control configured to control at least one of the plurality of schedulers to halt, step, or resume the given pipeline of the at least one of the plurality of schedulers for the data to enable debugging thereof. The system further includes a plurality of hardware accelerators configured to implement a series of tasks in accordance with a schedule provided by a respective scheduler in accordance with a command from the debug control. Each of the plurality of hardware accelerators is coupled to at least one of the plurality of schedulers to execute the instructions for the given pipeline and to a shared memory.

Abstract: In described examples, a circuit includes a multiplexer. The multiplexer receives an input voltage and a calibration signal. An analog-to-digital converter (ADC) is coupled to the multiplexer and generates an output code in response to the calibration signal. A storage circuit is coupled to the ADC and stores the input code representative of the calibration signal at an address corresponding to the output code. The stored input code includes an index value and a coarse value.

Abstract: In one example, an apparatus comprises an acoustic resonator, the acoustic resonator including: an electrode; and a piezoelectric layer on the electrode, in which the electrode covers entirely a surface of the piezoelectric layer, and the piezoelectric layer has a convex portion with a non-uniform thickness.

Abstract: A technique for convergence verification including receiving a data object representation of a first circuit block, receiving one or more assumptions associated with the first circuit block, identifying a synchronization scheme coupled to a port of the first circuit block, determining that the synchronization scheme is within a threshold flip-flop depth, identifying, based on the determination that the synchronization scheme is within the threshold flip-flop depth, a type of the synchronization scheme and a flip-flop depth between the synchronization scheme and the port, generating first convergence information for the first circuit block based on the identified type and flip-flop depth of the synchronization scheme, and outputting the generated convergence information.

Abstract: This invention involves a cache system in a digital data processing apparatus including: a central processing unit core; a level one instruction cache; and a level two cache. The cache lines in the second level cache are twice the size of the cache lines in the first level instruction cache. The central processing unit core requests additional program instructions when needed via a request address. Upon a miss in the level one instruction cache that causes a hit in the upper half of a level two cache line, the level two cache supplies the upper half level cache line to the level one instruction cache. On a following level two cache memory cycle, the level two cache supplies the lower half of the cache line to the level one instruction cache. This cache technique thus prefetches the lower half level two cache line employing fewer resources than an ordinary prefetch.

Abstract: A circuit includes an operational amplifier and a resistor network coupled to an output of the operational amplifier. The resistor network includes a first set of resistors coupled between the output of the operational amplifier and a first node of the resistor network, wherein the resistors of the first set are electrically connected in series with each other, a second set of resistors coupled between the first node and a second node of the resistor network, wherein the resistors of the second set are electrically connected in series with each other and include a first number of resistors, a third set of resistors coupled between the second node and a third node of the resistor network, wherein the third node is coupled to a first voltage, and wherein the resistors of the third set are electrically connected in parallel with each other and include a second number of resistors, and a resistor coupled between the first node and the second node and arranged in parallel with the second set of resistors.

Abstract: Methods, apparatus, systems and articles of manufacture to reduce bank pressure using aggressive write merging are disclosed. An example apparatus includes a first cache storage; a second cache storage; a store queue coupled to at least one of the first cache storage and the second cache storage and operable to: receive a first memory operation; process the first memory operation for storing the first set of data in at least one of the first cache storage and the second cache storage; receive a second memory operation; and prior to storing the first set of data in the at least one of the first cache storage and the second cache storage, merge the first memory operation and the second memory operation.