Abstract: Methods and apparatuses are described to convert analog signals to digital signals using a local charge averaging capacitor array (LCACA) in an analog-to-digital converter (ADC.) An apparatus includes a comparator. The comparator is configured with a first high input, a first low input, and is configure to receive a clock signal. A logic/latch block is configured to receive the clock signal and an output from the comparator. The logic/latch block is configured to output a control signal and a digital N-bit output signal. A local charge-averaging capacitor array (LCACA) is configured to receive the control signal and a reference voltage. An output of the LCACA is coupled to the first low input. The first LCACA is divided into a high sub-array and a low sub-array. The high sub-array is pre-charged to a high reference voltage and the low sub-array is pre-charged to a low reference voltage. The high reference voltage is greater than the low reference voltage.

Abstract: A method and apparatus for compressing data in a communication system by receiving uncompressed packet at a compressor of the communication system, segmenting the packet into a plurality of packet segments, estimating packet segment compression parameters for each of the plurality of packet segments and compressing the packet segments utilizing one or more of the estimated packet segment compression parameters that are estimated and adjusted based upon the signal characteristics of the uncompressed packet and a desired compression ratio.

Abstract: A periodic signal generator includes a resonant LC tank circuit that generates a periodic reference signal at a first frequency at a differential output thereof. A temperature-responsive frequency compensation module is electrically coupled to the differential output of the resonant LC tank circuit. This module includes a temperature dependent voltage control module that generates a temperature dependent control voltage and an array of switchable capacitive modules that is electrically coupled to a first node of the differential output of the resonant LC tank circuit and responsive to the temperature dependent control voltage and a plurality of switching coefficients. The array of switchable capacitive modules includes a fixed capacitor having a first terminal electrically coupled to the first node and a voltage-controlled variable capacitor having a first terminal electrically coupled to the first node.

Abstract: A digital filter for a frequency synthesizer (e.g., PLL, UFT) may include an analog-to-digital (ADC) converter, which is responsive to a control voltage at an input thereof, and a digital-to-analog (DAC) converter, which has an input responsive to a signal generated at an output of the ADC. An impedance element is provided between the DAC and ADC. The impedance element has real and reactive components, a first current carrying terminal electrically coupled to an output of the DAC and a second current carrying terminal electrically coupled to the input of the ADC. The impedance element can include a resistor and a capacitor, which are electrically connected in parallel. A gain device, such as a programmable multiplier, may also be provided, which has an input responsive to the signal generated at the output of the ADC and an output electrically coupled to the input of the DAC.

Abstract: A PLL includes a fractional divider to generate a periodic PLL output signal in response to REFHF. The fractional divider includes a digital control circuit (DDC) responsive to a digital control input signal and a multi-modulus divider (MMD), which is responsive to REFHF and a first digital control output signal generated by the DDC. A feedback divider (FD) is provided to generate a FD output signal in response to an MMD output signal generated by the MMD. A phase detector (PD) is provided to generate a PD output signal in response to the FD output signal and REF_CLK. A loop filter is provided to generate the digital control input signal in response to the PD output signal as modified by a noise cancellation signal (NCS). The NCS is generated to at least partially compensate for non-random deterministic noise in the MMD output signal.

Abstract: A wireless power-transfer system includes a power-transmitting device and a power-receiving device. A frequency generator generates a power-transmit frequency to stimulate transmit coil and transmit resonance adjuster, which generate a near-field electromagnetic radiation at an adjustable coupling frequency. The power-receiving device includes a receive coil and a receive resonance adjuster for receiving the near-field electromagnetic radiation when the receive coil is within a coupling region of the transmit coil. The receive resonance frequency may be modified by the receive resonance adjuster. In the wireless power-transfer system, one or both of the transmit resonance adjuster and the receive resonance adjuster is configured to adjust its corresponding frequency to be sufficiently less than the power-transmit frequency such that a monotonic transfer function is developed between the power-transmit frequency and the receive resonance frequency.

Abstract: Power control systems and power control devices may include a power control chip having a power control module configured to generate a power stage control signal, and an external power stage having a timing control module. The timing control module may be configured to receive the power stage control signal and generate a timing control signal controlling at least one switch to regulate an output voltage of the external power stage. The power control device further includes an auto-configuration module configured to communicate with the external power stage and request auto-configuration information from the external power stage. A related method of auto-configuring a power control system includes communicating auto-configuration information between at least one external power stage of a power control system and a power control chip, and configuring a setting of the at least one external power stage of the power control system based on the auto-configuration information.

Abstract: A wireless power enabled apparatus may comprise a wireless power receiver that includes a receive coil configured to generate an AC power signal responsive to a wireless power signal, a rectifier including a plurality of switches configured to receive the AC power signal and generate a DC rectified power signal, a regulator operably coupled with the regulator to receive the DC rectified power signal and generate an output power signal, and control logic configured to generate a communication signal responsive to adjusting an input impedance of the regulator. A method of operating a wireless power receiver includes generating a rectified voltage responsive to receiving a wireless power signal, generating an output voltage from the rectified voltage with a voltage regulator, and controlling the voltage regulator during a communication mode of wireless power receiver to modulate a characteristic of the voltage regulator with data for transmission to a wireless power transmitter.

Abstract: A power management integrated circuit incorporates (a) a microprocessor; (b) a non-volatile memory accessible by the microprocessor for storing programs executable by the microprocessor; (c) a random access memory accessible by the microprocessor; (d) an external interface which allows an external device to communicate with the power management integrated circuit; and (e) power regulators providing regulated output voltages from the power management integrated circuit, each power regulator being controllable by the microprocessor and the external interface over the register-controlled bus. A second external interface may be provided, which is used to provide a configuration file descriptive of power requirements of a system in which the power management integrated circuit is deployed. Such a system may include a system-on-a-chip (SOC) integrated circuit.

Abstract: An apparatus includes a phase locked loop (PLL) circuit configured to generate a PLL output signal from an oscillator signal and a control circuit configured to generate a measure of a difference between the PLL output signal and an input clock signal at a control output thereof. The apparatus further includes a dynamic range shifter circuit coupling the control output of the control circuit to a control input (e.g., a feedback divider control input) of the PLL circuit and configured to shift a dynamic range of the control output of the control circuit with respect to a dynamic range of the control input of the PLL circuit. The apparatus may be implemented with an oscillator, such as a MEMs oscillator, in a single chip.

Abstract: A peak current protection circuit includes a current sensing circuit configured to sense an operating current of a DC-DC converter, and an over-current detector operably coupled with the current sensing circuit. The over-current detector is configured to generate an over-current detect signal at a peak current limit that is that is independent of a voltage level of an output signal of the DC-DC converter. A method for providing over-current protection for a DC-DC converter includes sensing an operating current of a DC-DC converter at a first input of a comparator, sensing a reference current at a second input of the comparator, comparing the first input with the second input, and generating an over-current detect signal in response to the comparison such that a peak current limit for the DC-DC converter is independent of a voltage level of an output signal of the DC-DC converter.

Abstract: A method and apparatus provide signal compression for transfer over serial data links in a base transceiver system (BTS) of a wireless communication network. For the uplink, an RF unit of the BTS applies frequency domain compression of baseband signal samples, resulting from analog to digital conversion of received analog signals followed by digital downconversion, forming compressed coefficients. After transfer over the serial data link, the baseband processor then applies frequency domain decompression to the compressed coefficients prior to normal signal processing. For the downlink, the baseband processor applies frequency domain compression of baseband signal samples and transfers the compressed coefficients to the RF unit. The RF unit applies frequency domain decompression to the compressed coefficients prior to digital upconversion and digital to analog conversion, generating the analog signal for transmission over the antenna.

Abstract: In a distributed antenna system (DAS) and a local area network (LAN), a common communication infrastructure distributes data from radio-based and Internet-based sources. A radio equipment (RE) of the DAS interfaces to a LAN segment. For the downlink, a gateway maps radio signal data from a radio equipment controller (REC) and data packets from a switch to mixed-data frames using a radio data interface protocol for transmission in the DAS. At the RE, the signal data and data packets are retrieved from the mixed-data frames and provided to the air interface and LAN segment, respectively. For the uplink from the RE, the radio signal data from the air interface and the data packets from the LAN segment are mapped to mixed-data frames and transmitted to the gateway. The gateway retrieves the signal samples and data packets from the mixed-data frames for transfer to the REC and switch, respectively.

Abstract: A wireless power transmitter comprises a bridge inverter configured to receive a DC power signal and generate an AC power signal according to an operating frequency, a resonant tank configured to receive the AC power signal and generate an electromagnetic field responsive thereto, and control logic configured to cause the resonant tank to reconfigure and adjust its resonant frequency for a particular receiver type of a wireless power receiver with which a mutual inductance relationship is desired. A method comprises determining a receiver type for a wireless power receiver with which it is desired to establish a mutual inductance relationship for wireless power transfer, and generating a wireless power signal with a wireless power transmitter having an operating frequency and resonant tank that is adjusted for a particular receiver type.

Abstract: Integrated circuit devices include a packaged MEMS-based oscillator circuit, which is configured to support bidirectional frequency margining of a periodic output signal. This bidirectional frequency margining is achieved using a first signal to synchronize changes in a frequency of the periodic output signal and a second signal to control whether the changes in the frequency of the periodic output signal are incremental or decremental. In particular, the oscillator circuit may be configured so that each change in the frequency of the periodic output signal is synchronized to a corresponding first voltage transition of the first signal and a voltage level of the second signal may be used to control whether the changes in the frequency of the periodic output signal are incremental or decremental.

Abstract: The method and apparatus of the present invention provides for the compression of signal data having a low latency jitter while maintaining a target compression ratio and reasonable degradation, as is required by next generation systems. In accordance with the present invention, a method and apparatus are provided for compressing data in a communication system by receiving uncompressed packet at a compressor of the communication system, segmenting the packet into a plurality of packet segments, calculating signal sample bit-removal information for each of the plurality of packet segments and compressing the packet segments utilizing the signal sample bit-removal information that is calculated based upon the signal characteristics of the uncompressed packet and a desired target compression ratio.

Abstract: A method and apparatus provides OFDM signal compression for transfer over serial data links in a base transceiver system (BTS) of a wireless communication network. For the uplink, an RF unit of the BTS applies OFDM cyclic prefix removal and OFDM frequency transformation of the baseband signal samples followed by frequency domain compression of the baseband signal samples, resulting from analog to digital conversion of received analog signals followed by digital downconversion, forming compressed coefficients. After transfer over the serial data link, the baseband processor applies frequency domain decompression to the compressed coefficients prior to further signal processing.

Abstract: An oscillator circuit includes an adjustable frequency oscillator configured to free-run at a first frequency below a desired second target frequency. This adjustable frequency oscillator is configured to modulate a frequency of its periodic output signal upwards from the first frequency to the second frequency in response to a feedback bias current. A divider is also provided, which is configured to convert the periodic output signal to a reduced-frequency control signal. This reduced-frequency control signal is provided to a frequency-to-current (F2C) converter, which is configured to drive the adjustable frequency oscillator with the feedback bias current (e.g., pull-down current) in response to the reduced-frequency control signal.

Abstract: The present invention provides for EMI mitigation in switching circuitry, such as power converters, by implementing a controlled, non-random change in frequency in every cycle of switch control signals based on a static or dynamically changing modulation cycle. This permits frequency spreading across a wide range while avoiding excessive jitter between cycles and voltage dropouts common to randomized EMI control circuitry. Further, since it may be implemented digitally, some embodiments may avoid performance, size and power consumption problems experienced by mixed signal or analog switch control circuitry and EMI control circuitry. Further still, implementations of the present invention may mitigate EMI from a constant frequency source without the necessity of a variable frequency source, such as one generated by a VCO, to realize frequency variation.

Abstract: A wireless power receiver comprises a resonant tank configured to generate an AC power signal responsive to an electromagnetic field, a rectifier configured to receive the AC power signal and generate a DC output power signal, and control logic configured to control the resonant tank to reconfigure and adjust its resonant frequency responsive to a determined transmitter type of a wireless power transmitter. The control logic may operate the wireless power receiver as a multimode receiver having a first mode for a first transmitter type and a second mode for a second transmitter type. The resonant tank may exhibit a different resonant frequency for each of the first mode and the second mode. A method comprises determining a transmitter type for a wireless power transmitter desired to establish a mutual inductance relationship, and adjusting a resonant frequency of a resonant tank of a wireless power receiver.