Abstract: A wireless power enabled apparatus includes a wireless power receiver. The wireless power receiver includes a receive coil, a rectifier, a regulator, and a damping circuit. The receive coil is configured to generate an AC power signal responsive to a wireless power signal. The rectifier is configured to receive the AC power signal and generate a DC rectified power signal relative to a rectified ground signal. The regulator is operably coupled with the rectifier to receive the DC rectified power signal and generate an output voltage. The damping circuit is operably coupled between the DC rectified power signal and the rectified ground signal and in parallel with the regulator. The damping circuit is configured to suppress audible harmonics generated by the wireless power receiver at some loads by providing a damping impedance for the DC rectified power signal.
Abstract: A timing device that includes an OTP NVM, a first periodic signal generator operable to generate a periodic signal having a first frequency, a second periodic signal generator operable to generate a periodic signal having a frequency that is lower than the first frequency, and selection logic. In a first operating mode, the selection logic is configured to output the first periodic signal at an output terminal as long as a crystal clock feedback signal is received at the input terminal and output the second periodic signal when the crystal clock feedback signal is not received at the input terminal. In a second operating mode, the selection logic is configured to output the first periodic signal as long as a output enable signal is received at the input terminal and not provide any output at the output terminal when the output enable signal is not received at the input terminal.
Abstract: A wireless power receiver may include a receive coil configured to generate an AC power signal responsive to wireless power transfer from a wireless power transmitter, and control logic configured to detect misalignment of the receive coil and a transmit coil of the wireless power transmitter responsive to a determination of efficiency of wireless power transfer therebetween. A method for operating a wireless power receiver may include detecting misalignment between a receive coil and a transmit coil of a wireless power transmitter responsive to detecting monitoring a value indicative of efficiency of wireless power transfer between the wireless power transmitter and the wireless power receiver, and causing an indication to be provided to a user to assist with correcting the misalignment.
Type:
Grant
Filed:
September 26, 2014
Date of Patent:
April 17, 2018
Assignee:
Integrated Device Technology, Inc.
Inventors:
Jianbin Hao, Detelin Martchovsky, Chan Young Jeong, Arman Naghavi
Abstract: A system and method of wireless power transfer using a power converter with a bypass mode includes a power converter. The power converter includes a pulsed switch, a capacitor configured to supply a drive voltage to the pulsed switch, a first circuit configured to charge the capacitor when the power converter operates in a switched mode of operation, and, a second circuit configured to charge the capacitor when the power converter operates in a bypass mode of operation.
Type:
Grant
Filed:
October 27, 2015
Date of Patent:
April 3, 2018
Assignee:
Integrated Device Technology, Inc.
Inventors:
Rosario Pagano, Christopher Joseph Daffron, Angel Maria Gomez Arguello, Siamak Abedinpour
Abstract: A multimode receiver can include on or more of an over-voltage protection circuit or a high frequency mode switch. As such, some embodiments of a multi-mode receiver includes a rectifier; a high frequency circuit coupled to the rectifier; a low frequency circuit coupled to the rectifier; and a switching circuit coupled to disable at least a portion of the low frequency circuit while the multi-mode receiver operates in high frequency mode. In some embodiments, the multimode receiver further includes a high-voltage protection circuit coupled to the high frequency circuit that detunes the high frequency circuit when a high-voltage condition is detected.
Abstract: A switching regulator is presented. An embodiment of the switching regulator can include a high switch coupled between an input voltage and a switched output; a low switch coupled between the switched output and a ground; and a ringing switch coupled between a capacitor and the switched output, wherein the ringing switch is closed prior to transition into a tristate where both the high switch and the low switch are open.
Abstract: Disclosed is a circuit having a high speed laser driver circuit, a semiconductor laser electrically connected to the high speed laser driver circuit, and an adjustable termination circuit electrically connected between the high speed laser driver circuit and the semiconductor laser, where the adjustable termination circuit is configured to control an output impedance seen by the semiconductor laser as a function of an input current provided to the adjustable termination circuit.
Abstract: A rectifier circuit can include a plurality of FETs arranged as a rectifier; and a start-up circuit applied to each of the plurality of FETs that turn each of the FETs off during a circuit startup period, wherein the start-up circuit provides a large impedance for low power dissipation during normal operation of the rectifier.
Abstract: A transmitter/receiver that includes a wireless power receiving mode and a data transmission mode. In the wireless power receiving mode, the transmitter/receiver receives wireless power through and coil and provides power to a load. In data transmission mode, the transmitter/receives drives the coil according to data to transmit data.
Abstract: A frequency synthesizer with microcode control that allows one or more programmable circuits of a frequency synthesizer system to be programmed using a plurality of microcode instructions. A method includes, setting a frequency synthesizer system to operate in a microcode mode, programming the frequency synthesizer system for microcode execution of a plurality of microcode instructions and executing the plurality of microcode instructions at the frequency synthesizer system to control one or more behaviors of one or more programmable circuits of the frequency synthesizer system.
Type:
Grant
Filed:
July 14, 2016
Date of Patent:
December 19, 2017
Assignee:
Integrated Device Technology, Inc.
Inventors:
Chung-Yu Wu, Wei-Ching Chan, John Hsu, Cheng Wen Hsiao
Abstract: A method includes separating phase of Local Oscillator (LO) signals generated by individual Voltage Controlled Oscillators (VCOs) of a coupled VCO array through varying voltage levels of voltage control inputs thereto. The method also includes coupling the individual VCOs of the coupled VCO array to one another in a closed, circular configuration to increase phase difference between the phase separated LO signals generated by the individual VCOs compared to a linear configuration of the coupled VCO array. Further, the method includes mixing outputs of the individual VCOs of the circular coupled VCO array with signals from antenna elements of an antenna array to introduce differential phase shifts in signal paths coupled to the antenna elements during performing beamforming with the antenna array.
Type:
Grant
Filed:
March 17, 2014
Date of Patent:
December 5, 2017
Assignee:
Integrated Device Technology, Inc.
Inventors:
Christopher T. Schiller, Jonathan Kennedy
Abstract: A wireless power transmitter may include a bridge inverter and a plurality of parallel paths operably coupled to the bridge inverter. Each path includes a resonance tank including a transmit coil coupled with at least one resonance capacitor, a first switch serially coupled with the resonance tank and switching node A of the bridge inverter, a first clamping element in parallel with the first switch, a second switch serially coupled with the resonance tank and switching node B of the bridge inverter, and a second clamping element in parallel with the second switch. A method includes generating a wireless power signal through a used coil in a first parallel path, and clamping a parasitic voltage generated in at least one unused coil in at least one additional parallel path through a clamp element across a switch in the at least one parallel path for the at least one unused coil.
Type:
Grant
Filed:
March 26, 2015
Date of Patent:
December 5, 2017
Assignee:
Integrated Device Technology, Inc.
Inventors:
Gustavo J. Mehas, Nicholaus W. Smith, Adam M. Bumgarner
Abstract: A packaged integrated circuit device includes a first driver, which has a first pair of differential output terminals and a first common-mode sensing terminal, and a second driver, which has a second pair of differential output terminals and a second common-mode sensing terminal. The second driver can be a smaller scaled replica of the first driver. A comparator and a reference signal generator are provided. The comparator is configured to compare first and second common-mode voltage signals developed at the first and second common-mode sensing terminals, respectively, and the reference signal generator is configured to provide the first and second drivers with a reference voltage having a magnitude that varies in response to changes in a signal generated at an output terminal of the comparator. This variation in the magnitude of the reference voltage supports a built-in adaptive response to changes in source-side termination in HCSL driver/receiver circuits.
Abstract: A system and method of wireless power transfer using a two half-bridge to one full-bridge switchover includes a wireless power transfer system. The wireless power transfer system includes a controller, first and second transmitters coupled to the controller, the first and second transmitters being coupled to one another by an electrical connection, and a switch coupled between the electrical connection and a voltage rail. When the switch is closed, the controller operates the first and second transmitters in a two half-bridge mode. When the switch is open, the controller operates the first and second transmitters in a one full-bridge mode.
Abstract: Packaged integrated circuit devices include an oscillator circuit having a resonator (e.g., quartz crystal, MEMs, etc.) associated therewith, which is configured to generate a periodic reference signal. A built-in self-test (BIST) circuit is provided, which is selectively electrically coupled to first and second terminals of the resonator during an operation by the BIST circuit to test at least one performance characteristic of the resonator, such as at least one failure mode. These test operations may occur during a built-in self-test time interval when the oscillator circuit is at least partially disabled. In this manner, built-in self-test circuitry may be utilized to provide an efficient means of testing a resonating element/structure using circuitry that is integrated within an oscillator chip and within a wafer-level chip-scale package (WLCSP) containing the resonator.
Type:
Grant
Filed:
September 30, 2015
Date of Patent:
October 17, 2017
Assignee:
Integrated Device Technology, Inc.
Inventors:
James Bryan Northcutt, Stephen Amar Tibbitts, Robert A. Gubser, Bruce Edward Clark, John William Fallisgaard, Kenneth Astrof
Abstract: Overvoltage protection circuits include a combination of an overvoltage detection circuit and a voltage clamping circuit that inhibits sustained overvoltage conditions. An overvoltage detection circuit can include first and second terminals electrically coupled to first and second power supply signal lines, respectively. This overvoltage detection circuit may be configured to generate a clamp activation signal (CAS) in response to detecting an excessive overvoltage between the first and second power supply signal lines. This CAS is provided to an input of the voltage clamping circuit, which is electrically coupled to the first power supply signal line and configured to sink current from the first power supply signal line in response to the CAS. The voltage clamping circuit may be configured to turn on and sink current from the first power supply signal line in-sync with a transition of the CAS from a first logic state to a second logic state.
Type:
Grant
Filed:
December 19, 2014
Date of Patent:
October 17, 2017
Assignee:
Integrated Device Technology, Inc.
Inventors:
Alan Wolfram Glaser, Tak Kwong Wong, Al Fang, Roland Thomas Knaack, Jon Roderick Williamson
Abstract: A method includes injecting a reference input signal into each Voltage Controlled Oscillator (VCO) of a number of VCOs forming a coupled VCO array to reduce a level of injection energy required therefor. The reference input signal is configured to control operating frequency of the coupled VCO array. The method also includes utilizing a phase shift circuit: between individual VCOs of the coupled VCO array and/or in a path of injection of the reference input signal into one or more VCO(s) of the individual VCOs, and mixing outputs of the number of VCOs with signals from antenna elements of an antenna array to introduce differential phase shifts in signal paths coupled to the antenna elements during performing beamforming with the antenna array. Further, the method includes reducing a phase-steering requirement of the coupled VCO array during the beamforming based on the utilization of the phase shift circuit.
Type:
Grant
Filed:
March 17, 2014
Date of Patent:
October 3, 2017
Assignee:
Integrated Device Technology, Inc.
Inventors:
Christopher T. Schiller, Jonathan Kennedy
Abstract: An apparatus having a first circuit and a second circuit. The first circuit may be configured to buffer an input signal received as a single-ended signal from a data bus connected between a memory channel and a memory controller. The second circuit may be configured to condition the input signal relative to a reference voltage to generate a differential signal. The reference voltage may be isolated from the second circuit in response to a transition from a power down condition to a power on condition.
Abstract: An apparatus includes a first circuit, a second circuit, and a third circuit. The first circuit may be configured to (i) reduce a current value in a sequence of input values that have been carried on a single-ended line of a data bus coupled to a memory channel to generate a version of the current value, and (ii) reduce a first reference voltage to generate a second reference voltage. The second circuit may be configured to slice the current value with respect to the first reference voltage to generate a first intermediate value. The third circuit may be configured to slice the version of the current value with respect to the second reference voltage to generate a second intermediate value. The first intermediate value and the second intermediate value generally define a sliced value of the current value.
Abstract: An integrated circuit to remove jitter from a clock signal includes an integrated circuit die. The integrated circuit die includes a signal comparator. The signal comparator is configured to determine a frequency difference between a jittery input clock signal and a correction signal. A digital low pass filter is coupled to receive and filter the frequency difference and to provide a filtered output signal. A free running crystal-less oscillator produces a reference signal. A fractional output divider is coupled to the free running crystal-less oscillator and the digital low pass filter. The fractional output divider utilizes the filtered output signal to establish a value to divide the reference signal by to obtain a clean output clock signal. The clean output clock signal is fed back to the signal comparator and is used as the correction signal.