Abstract: Methods, systems and computer program products are provided which utilize luminance in the reduction in resolution of high-resolution values of the color components to provide reduced-resolution values of the color components. These methods, systems and computer program products preferably reduce the resolution of the high-resolution-value of the color components for a picture element to provide reduced-resolution values based upon the difference in luminance between the high-resolution values of the color components and the reduced-resolution values of the color components. Preferably, the difference between the luminance of the high-resolution values of the color components and the reduced-resolution values of the color components is minimized.

Abstract: An apparatus and method for sharing cache lines within a split data/code cache is provided. The invention utilizes cache snoop and state control, coupled to both a data cache and a code cache, which allows the data cache to snoop fetches to the code cache, and allows the code cache to snoop reads and writes to the data cache. In addition, cache snoop and state control modifies the state of a particular cache line within both of the caches according to the MESI cache coherency protocol to allow a single cache line to reside in both the data cache, and the code cache, in a Shared state. The invention allows the shared cache line to be fetched from the code cache, and retrieved from the data cache, until it is overwritten or modified in the data cache. In one embodiment, an instance of a cache line within either the code or data cache can be snarfed into the other cache, and marked as shared.

Abstract: A method forms, in a CMOS semiconductor substrate, P- and N-wells having independently optimized field regions and active regions. In one embodiment, P- and N-wells are formed by (i) creating in successive steps the field regions of the P- and N-wells; (ii) creating an oxide layer over the field regions, (iii) creating in successive steps the active regions. The method achieves the P- and N-wells without increasing the number of photoresist masking steps. In addition, optical alignment targets (OATs) are optionally formed simultaneously with these P- and N-wells without increasing the total number of process steps.

Abstract: An image generation system is provided which includes a processing element array comprised of a plurality of processing elements, wherein the processing elements are interconnected such that processing elements in said processing element array communicate directly with each other. The processing elements are divided into a plurality of panels. Global bus interconnection means allow for communicating information on one panel communications bus to the other panel communication buses. Validity flags of the global bus interconnection indicate which bytes are valid on the bus. A microcode cache may also be included.

Abstract: A multi-error detector uses single byte error correcting-double byte error detecting codes but detects some multiple errors including double, triple, quadruple and more errors in a code. To detect the multiple errors, the multi-error detectors uses error pointer and a syndrome which are generated by error correction circuitry. Multiple errors are indicated when the syndrome indicates an error and either none or more than one of the error pointers are set. In one embodiment, a tree of half adders has least significant output bits from the adders coupled to input terminals of subsequent adders in the tree. Circuit logic detects multiple errors from the least significant output bit of the last adder in the tree and the more significant output bits from all the adders.

Abstract: The present invention uses a clean semiconductor substrate, typically in wafer form, and applies to the surface of the semiconductor a wet chemical that is suspected of containing a contaminant. After drying of the wet chemical, a high temperature, low pressure chemical vapor deposition of a semiconductor material is performed. Metal contaminants that exist on the surface of the semiconductor substrate act as seeds to initiate crystal growth of the semiconductor material that is being deposited. Due to the enhanced crystal growth of the semiconductor material at locations corresponding to positions of the metal contaminant on the semiconductor substrate, a visual inspection of the resulting surface of the semiconductor will indicate the presence of a metal contaminant.

Abstract: An adaptable, programmable convolutional interleaving and de-interleaving system uses less space in an integrated circuit than prior art techniques, and is scalable for wide variety of values of I and M. The coder comprises a coder input receiving a stream of data in time with a clock, the stream of data being supplied in units of data such as bytes, and a coder output which supplies the interleaved or de-interleaved data. A single port RAM having an address input, a data input coupled to the coder input, and a data output coupled to the coder output is included. An address generator is coupled with the clock, and supplies a sequence of addresses to the address input in time with the clock. The sequence of addresses implements a convolutional pattern having cells with a depth equal to M units of data and having a number of rows I+1. Each row, based on an index i going from 0 to 1, includes i cells.

Abstract: A method for maintaining an alignment mark on a semiconductor substrate includes formation of an opening called a "protective window," that is sufficiently deep to ensure that an alignment mark formed at the bottom of the preventive window remains intact during planarization, e.g. by chemical mechanical polishing. Prior to planarization, the protective window has a height that is larger than a predetermined distance known to be sufficient to protect the alignment mark. The protective window is created by etching away one or more layers, such as a layer of metal and a layer of polysilicon simultaneously with etching steps normally required to create patterns for electronic devices on the substrate. Such creation of a protective window prior to planarization eliminates the need for masking and etching steps conventionally used after planarization to recover an alignment mark.

Abstract: A circuit and a method for providing a power supply voltage to a memory circuit during a memory data retention test are provided. In such a circuit, a first power supply terminal and a second power supply terminal are provided together with a plurality of circuit elements, which are coupled to form a current path between the first and second power supply terminals, such that each circuit element contributes a predetermined voltage drop between the first and second power supply terminals when a current flows in said current path. In addition, a shunt device having a control terminal and coupled across one or more of said circuit elements is provided. The control terminal receives a control signal, such that when the control signal is asserted, the shunt device equalizes a voltage across said one or more of said circuit elements. The memory circuit draws its power supply voltage from the second power supply terminal.

Abstract: An improved flip-chip bond connection and bonding method uses a "press fit" bond between a set of bond pad bumps or projections on a semiconductor chip and corresponding set of substrate bumps or projections on a substrate to self-align the chip with the substrate and enable flip-chips to be inexpensively bonded to substrates or packages with greater accuracy and a smaller pad pitch than previously achieved. In the method after normally one of the sets of bond pad bumps or substrate bumps has been cooled to shrink or contract so that the facing surfaces of each of the pad bumps and substrate bumps can be interdigitated, the chip and substrate are moved together so that the respective bumps are in a substantially common plane. The one cooled set of bumps is then warmed to expand that set of bumps sufficiently to form a lateral press-fit force between the facing surfaces, physically securing and electrically connecting the respective sets of bumps.

Abstract: A structure and a method are provided to implement a reset scheme for an integrated circuit supporting a variety of testing and debugging equipment. The control and I/O pins of the integrated circuit are each set to a high impedance state when the signals of a reset pin and a mode pin are both asserted. If the signal on the mode pin remains asserted at the time the signal on the reset pin is negated, the control and I/O pins of the integrated circuit remain in the high impedance state until the next time the signal on the reset pin is asserted. Otherwise, the control and I/O pins of the integrated circuits are enabled upon negation of the signal on the reset pin. In one embodiment, the mode pin is multiplexed with an pin used for receiving interrupt signals during functional operation.

Abstract: Methods, apparatus and computer program products for applying texture to the surfaces of objects in graphics images utilizing texture patterns organized into blocks of texels. Each block of texels is preferably compressed using a block-oriented compression technique and then compressed further using entropy coding. Multiple processing elements rendering an image make requests for texels by address. The texel addresses are converted to block addresses, and the block addresses are consolidated and redundant requests are eliminated. The blocks are retrieved from texture pattern memory, performs entropy decoding, and transfers the data to the processor array such that the likelihood of redundant retrieval of texture data is reduced. The processing elements utilize the retrieved texture data for calculation of pixel values utilizing the texture information.

Abstract: A method and apparatus for eliminating the setup time typically required for Booth recoding logic is provided. Interlock circuitry detects when a second multiply instruction specifies that the product of a previous multiply instruction is to be used as the multiplier input to the Booth recoding logic. The interlock logic controls mux inputs to both the multiplier path, and the multiplicand path. When the interlock logic detects such a multiplier dependency, the product of the previous multiply instruction is provided to the multiplicand path, and the multiplicand is provided to the multiplier path. The multiplier for the second multiply instruction can therefore be provided to the Booth recoding logic, before the product of the previous multiply instruction is available. The Booth recoding logic is therefore setup, prior to execution of the second multiply instruction.

Abstract: An error correction decoder which includes a syndrome calculator, an error locator polynomial calculator, a standard error locator polynomial calculator, an error transform calculator and an inverse error transform calculator. These error correction decoder calculators provide a pipelined architecture for performing Reed-Solomon error correction calculations quickly. The error locator polynomial calculator includes an R-Q calculator, a .lambda.-.mu. calculator, an R-Q degree calculator and a trigger circuit. These calculators and the trigger circuit can be implemented each as a plurality of generic cells. The number of generic cells can be changed to construct Reed-Solomon circuits for different Reed-Solomon codes. The R-Q, .lambda.-.mu. and R-Q degree calculators provide adaptive circuits that use switches and multiplexors, for example, to adapt to perform appropriate calculations based upon the nature of the error correction polynomials applied to the inputs of the calculators. The R-Q, .lambda.-.mu.

Abstract: An apparatus and method for smart configuration of functional blocks within a semiconductor device is provided. A fuse array contains a plurality of fuses that are blown in manufacturing to enable/disable functional blocks on the semiconductor device. A control unit reads the state of the fuses, and logically merges the fuse states with a default configuration for the functional blocks. The result of the merge operation is stored in a feature control register that individually enables/disables the functional blocks. The control unit also receives a write command from an external source that modifies the feature control register, after the device is shipped from the manufacturer. The control unit selectively blocks writes to the feature control register that attempt to enable/disable functional blocks that should not modified.

Abstract: A process for manufacturing a BiCMOS integrated circuit is implemented by adapting the masking and doping steps used in forming CMOS devices. Thus simultaneous formation of both CMOS and bipolar device structures eliminates the need for any additional masking or process steps to form bipolar device structures. Collector regions 20 of NPN transistors are formed simultaneously with N-wells 18. Collector regions of PNP transistors, if required, are formed simultaneously with P-wells 16. Base regions 24 of the bipolar transistors are formed using threshold voltage implant steps and/or lightly doped drain implant steps of PMOS transistors. Emitter regions 59 are formed, when using a single polysilicon CMOS process, simultaneously with the CMOS gates 72, 74. When employing a double polysilicon CMOS process, the emitter regions 59 are formed concurrently with the second polysilicon layer interconnect structure and/or source/drain regions 50,52 of NMOS transistors.

Abstract: An error correction decoder which includes a syndrome calculator, an error locator polynomial calculator, a standard error locator polynomial calculator, an error transform calculator and an inverse error transform calculator. These error correction decoder calculators provide a pipelined architecture for performing Reed-Solomon error correction calculations quickly. In the inverse error transform calculator, a method for calculating inverse error transforms is used. The method is adapted to receive error transforms in the same sequence as the error transforms are output by the error transform calculator without the need for buffering between the error transform calculator and the inverse error transform calculator and without the addition of substantial timing delays. In particular, the inverse error transform calculator is adapted to receive error transforms in the sequence E.sub.0, E.sub.1 . . . E.sub.N-1.

Abstract: A method and apparatus for handling interrupts after transition of a mask flag is provided. In x86 processors, if the IF flag is set, interrupts are to be handled. However, if the IF flag transitions from a clear state to a set state, and the instruction which sets the IF bit is an STI instruction, then a pending interrupt is to be delayed for one instruction, unless the following instruction is a floating point instruction, and then the interrupt is to be handled immediately. The invention allows an interrupt to cause a branch to an exception handler if the IF bit is set. The exception handler determines whether the prior instruction was an STI instruction, and whether the prior state of the IF bit was clear. If both these conditions are true, the exception handler branches back to the main program. If either condition is not true, the exception handler branches to an interrupt service routine.

Abstract: Removable extension areas electrically connected to the original die bond pad allow for testing connections to be made. After removal of the extension areas, the circuitry below the region of the extension areas can be seen through a microscope. The use of perforations and/or underlayer sections can aid in the removal of the extension areas. Underlayer sections may comprise a metal that forms an intermetallic interaction with the metal layer of the extension areas.

Abstract: An error correction decoder which includes a syndrome calculator, an error locator polynomial calculator, a standard error locator polynomial calculator, an error transform calculator and an inverse error transform calculator. These error correction decoder calculators provide a pipelined architecture for performing Reed-Solomon error correction calculations quickly. The error transform calculator includes a plurality of error transform processing circuits. The error transform calculator uses multiplexors to provide an adaptive input mechanism that adapts to receive known error transforms in an appropriate one of the error transform processing circuits. The multiplexors are used to form appropriate shift and feedback paths that are adapted to calculate unknown error transforms from the received known error transforms. The calculations are performed using multipliers and adders. Memory elements that store coefficients of a standard error locator polynomial are also used.